Low Power Design Methodology

Due to widespread application of portable electronic devices and the evaluation of microelectronic technology, power dissipation has become a critical parameter in low power VLSI circuit designs. In emerging VLSI technology, the circuit complexity and high speed imply significant increase in the power consumption. In low power CMOS VLSI circuits, the energy dissipation is caused by charging and discharging of internal node capacitances due to transition activity, which is one of the major factors that also affect the dynamic power dissipation. The reduction in power, area and the improvement of speed require optimization at all levels of design procedures. Here various design methodologies are discussed to achieve our required low power design concepts

Low Power Design for D Flip Flop

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Course grained low power design flow using UPF

Increased system complexity has led to the substitution of the traditional bottom-up design flow by systematic hierarchical design flow. The main motivation behind the evolution of such an approach is the increasing difficulty in hardware realization of complex systems. With decreasing channel lengths, few key problems such as timing closure, design sign-off, routing complexity, signal integrity, and power dissipation arise in the design flows. Specifically, minimizing power dissipation is critical in several high-end processors. In high-end processors, the design complexity contributes to the overall dynamic power while the decreasing transistor size results in static power dissipation. This research aims at optimizing the design flow for power and timing using the unified power format (UPF). UPF provides a strategic format to specify power-aware design information at every stage in the flow. The low power reduction techniques enforced in this research are multi-voltage, multi-threshold voltage (Vth), and power gating with state retention. An inherent design challenge addressed in this research is the choice of power optimization techniques as the flow advances from synthesis to physical design. A top-down digital design flow for a 32 bit MIPS RISC processor has been implemented with and without UPF synthesis flow for 65nm technology. The UPF synthesis is implemented with two voltages, 1.08V and 0.864V (Multi-VDD). Area, power and timing metrics are analyzed for the flows developed. Power savings of about 20 % are achieved in the design flow with \u27multi-threshold\u27 power technique compared to that of the design flow with no low power techniques employed. Similarly, 30 % power savings are achieved in the design flow with the UPF implemented when compared to that of the design flow with \u27multi-threshold\u27 power technique employed. Thus, a cumulative power savings of 42% has been achieved in a complete power efficient design flow (UPF) compared to that of the generic top-down standard flow with no power saving techniques employed. This is substantiated by the low voltage operation of modules in the design, reduction in clock switching power by gating clocks in the design and extensive use of HVT and LVT standard cells for implementation. The UPF synthesis flow saw the worst timing slack and more area when compared to those of the `multi-threshold\u27 or the generic flow. Percentage increase in the area with UPF is approximately 15%; a significant source for this increase being the additional power controlling logic added

"WindFi" - a renewable powered base station for rural broadband

The HopScotch rural wireless broadband access test bed uses a network of low power base stations, powered by renewable energy sources to provide a low-cost rural broadband solution. In this paper we discuss the low power design aspects of the HopScotch base station and the impact on the required generation potential of renewable sources, battery bank sizing and the use of tracking PV arrays

Exploring Energy-Efficient Reconfigurable Architectures for DSP Algorithms

Future hand-held multimedia terminals require a very high performance on a very small energy budged. Such devices can only be realized if their entire system is energy cognisant. In this paper a reconfigurable systems-architecture for mobile multimedia systems is introduced. The Field Programmable Function Array (FPFA) is discussed in detail. Several digital signal processing algorithms are discussed and mapped on the FPFA. Also,the power radius theory about low-power design is introduced

Low-power Design of a Neuromorphic IC and MICS Transceiver

abstract: The first part describes Metal Semiconductor Field Effect Transistor (MESFET) based fundamental analog building blocks designed and fabricated in a single poly, 3-layer metal digital CMOS technology utilizing fully depletion mode MESFET devices. DC characteristics were measured by varying the power supply from 2.5V to 5.5V. The measured DC transfer curves of amplifiers show good agreement with the simulated ones with extracted models from the same process. The accuracy of the current mirror showing inverse operation is within ±15% for the current from 0 to 1.5mA with the power supply from 2.5 to 5.5V. The second part presents a low-power image recognition system with a novel MESFET device fabricated on a CMOS substrate. An analog image recognition system with power consumption of 2.4mW/cell and a response time of 6µs is designed, fabricated and characterized. The experimental results verified the accuracy of the extracted SPICE model of SOS MESFETs. The response times of 4µs and 6µs for one by four and one by eight arrays, respectively, are achieved with the line recognition. Each core cell for both arrays consumes only 2.4mW. The last part presents a CMOS low-power transceiver in MICS band is presented. The LNA core has an integrated mixer in a folded configuration. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. The SRO is used in a wakeup RX for the wake-up signal reception. The all digital frequency-locked loop drives a class AB power amplifier in a transmitter. The sensitivity of -85dBm in the wakeup RX is achieved with the power consumption of 320µW and 400µW at the data rates of 100kb/s and 200kb/s from 1.8V, respectively. The sensitivities of -70dBm and -98dBm in the data-link RX are achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600µW and 1.5mW at 1.2V and 1.8V, respectively.Dissertation/ThesisPh.D. Electrical Engineering 201

Low Power Design Of Asynchronous Fine-Grain Power-Gated Logic

In technology improvement power dissipation has one of the major factor well known short circuit dissipations, leakage dissipations and dynamic switching dissipations are major power dissipation sources of CMOS Chips. For reducing power dissipation in CMOS logic blocks various techniques were there among these techniques most effective new technique implemented with low power dissipation. That is “low power design of Asynchronous fine-grain power gated logic”(LPAFPL). Low power AFPL is a new logic family. It consist of ECRL (efficient charge recovery logic gate), Pipeline system, C-element and Partial Charge Reuse mechanism (PCR). Each pipeline stage is comprised efficient charge recovery logic gate gains power and it is became active when useful computations are there and does not requires power at idle stage. Thus gives negligible leakage power dissipation. PCR is the output node of the ECRL logic, To evaluate the CMOS logic circuit level. Then it automatically reduced the power dissipation in complete evaluation of CMOS circuits

Low Power system Design techniques for mobile computers

Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, sys tem decomposition, communication and MAC protocols, and low power short range net works