Design of an Advanced Programmable Current-Source Gate Driver for Dynamic Control of SiC Device

Silicon carbide (SiC) power devices outperform Silicon-based devices in operational voltage levels, power densities, operational temperatures and switching frequencies. However, the gate oxide of SiC-based device is more fragile compared with its Si counterpart. The vulnerability of the gate oxide in SiC power devices requires the development of a gate driver that is able to have more control during the turn-on and turn-off process. This paper proposes an innovative current-source gate driver where the gate current can be fully programmed. The novelty of the gate driver is that the dynamic switching transients and the static on/off-state can be controlled independently. In order to achieve this approach, a signal decomposition and reconstruction technique is proposed to apply the separate control over the dynamic switching transient and the static on/off-state gate voltage respectively. The fundamental principle of the proposed circuit is verified in simulation. In addition, a prototype of the active gate driver has been built and tested to validate the effectiveness of the flexible control over the gate voltage

THE IMPACT OF LOW DUTY CYCLES IN HIGH FREQUENCY GATE DRIVER

This study is about the impact of low duty cycle in high frequency gate driver. Duty cycle is important for power electronic device to make it work efficiently. Thus, the objective for this project is to design the lowest duty cycle as possible in order to observe the impact on gate driver and converter. The different value of duty cycle will be applied to two different types of gate drivers which are conventional gate driver and resonant gate driver. By applying pulse width modulation (PWM) to gate driver switches, it will be determined the duty cycle of the gate driver. The PWM is fed directly to both switches on drive circuit to activate the power MOSFET. Thus, by changing the PWM value, it will affect the duty cycle of the gate driver and resultant power MOSFET, M3. Therefore, the different output voltage, output current and operation mode of buck converter can be determined from the duty cycle at M3. Thus, the lowest duty cycle can be obtained with respect to the buck converter's performance. Some basic calculations and relationship between duty ratios to the converter will be explored in this work. However, the dead time application needs to be considered to avoid cross conduction for gate driver circuit to improve the efficiency of the driver. The findings show the lowest duty cycle of high frequency CGD is 16 % whilst 15 % forRGD

CMOS Gate Drive IC With Embedded Cross Talk Suppression Circuitry For Power Electronic Applications

Electric Vehicle (EV) propulsion systems are typically driven by three phase-leg motor drives, which consist of a pair of power devices. Each one of these power devices must be driven by a gate driver chip to operate efficiently. The proposed gate driver solution considers driving SiC devices and has been developed to increase the efficiency of such devices, which requires new gate driver solutions that can properly handle the high switching speeds of these devices. The higher switching speeds seen in SiC devices have brought forth a new problem: cross-talk. Cross-talk can be seen in the false switching of the partner device of a phase-leg as the driven device is being switched. Therefore, crosstalk suppression circuitry must be considered when developing a new gate driver solution. The proposed gate driver includes embedded cross talk suppression. The new gate driver topology will be presented and will show the cross talk suppression operation

Design, Layout, and Testing of a Silicon Carbide-based Under Voltage Lock-out Circuit

Silicon carbide-based power devices play an increasingly important role in modern power conversion systems. Finding a means to reduce the size and complexity of these systems by even incremental amounts can have a significant impact on cost and reliability. One approach to achieving this goal is the die-level integration of gate driver circuitry with the SiC power devices. Aside from cost reductions, there are significant advantages to the integration of the gate driver circuits with the power devices. By integrating the gate driver circuitry with the power devices, the parasitic inductances traditionally seen between the gate driver and the switching devices can be significantly reduced, allowing faster switching speeds, which in turn leads to higher efficiencies, less aggressive thermal management requirements, and physically smaller passives. Collaborators from Toyota, Cree, the University of Arkansas, Oak Ridge National Labs, and Arkansas Power Electronics International have designed, fabricated, and tested a custom gate driver circuit implemented in a low-voltage SiC-based process by Cree. This gate driver implementation is the first step toward the goal of a completely integrated system. One key sub-component of this gate driver is the Under Voltage Lock-Out (UVLO) circuit, which asserts a signal whenever the supply voltage to the die falls below a set threshold and allows circuitry both on- and off-chip to take steps to prevent damage to the system. The work presented herein is the design, layout, and testing of a UVLO circuit implemented in the low-voltage silicon carbide process available from Cree. The UVLO was demonstrated to operate over a temperature range between -55 oC and 300 oC. An overview of the gate driver design, the fabrication process, and the trade-offs made during the UVLO circuit design process will be presented, as well as the integrated circuit layout workflow. A synopsis of the die testing apparatus and results will also be provided

Bi-direction transmissible gate driver on array

Background In recent years, gate driver using amorphous silicon (a-Si) technology for the TFT-LCD has become the main stream due to the mature manufacturing, low-cost processing, and elimination of the gate driver ICs [1],[2]. However, it’s still three challenges of design the integrated gate driver by a-Si encounters which are the low field-effect mobility, low reliability issue under high voltage stress, and the lack of P-type transistor. Please click Additional Files below to see the full abstract

Design and Implementation of a High Temperature Fully-Integrated BCD-on-SOI Under Voltage Lock Out Circuit

As concern about the environment has grown in recent years, alternatives in the automotive industry have become an important topic for researchers. One alternative being considered is electric vehicles, which utilize electric motors. DC/AC inverters and DC/DC power converters control these electric motors. A logic circuit is needed to power these converters; however, the logic generators inherently operate at a voltage too low to power the motors. A device known as the gate driver is the interface between the logic generators (or microcontroller) and the power devices (power converter). The gate driver provides the power needed to drive the power devices. Circuits are susceptible to voltage and temperature changes though. For this reason, protection circuits must be implemented as an integral part of the gate driver circuits. The Under Voltage Lock Out (UVLO) circuit provides important detection of under voltage conditions in the power supply thus preventing malfunctions. There are multiple power supplies in the gate driver circuit, and it is important to monitor all of these supplies for both surges and reductions in power. If the power supply should drop below the threshold (nominally 80%) there could be issues in the gate driver’s functionality. Since the gate driver will be located under the hood of a hybrid electric vehicles, operating temperatures can reach extremely high values. For this reason, circuit designs must provide reliable operation of the circuits in an extreme environment

The Experimental Analysis of Predictive Control Scheme in High Frequency Gate Driver Design

Predictive Dead Time Control Scheme is used in gate driver to overcome the problems relating to the td. This control scheme applies the prediction concept based on the feedback output from the circuit to predict and reduce the tdon the switching cycle of the gate driver. Therefore by using the application of the predictive dead time control scheme, the problem related with the td can be minimized

Hardware design of magnetically isolated gate driver using insulated gate bipolar transistor (IGBT)

This paper presents the hardware design of compact H-bridge magnetically isolated gate driver using Insulated Gate Bipolar Transistor (IGBT) as power device. The new Gate Driver (GD) circuit is tested experimentally with various switching frequency to observe the performance of the circuit. The compact H-Bridge is design using Proteus in one circuit board with two layers Printed Circuit Board (PCB). Switching transients of the IGBT is analyzed based on the capabilities of the GD circuit

GaN HEMT gate-driver for achieving high power converter integration levels

This work proposes a solution for implementing an isolated gate driver for GaN HEMTs based on the previous topology for SiC power MOSFETs. The isolation of the gate driver is realised by the single transformer topology with double winding in the secondary side. The Bi-level HF Amplitude Modulation scheme is retained to avoid the core saturation as well as providing simultaneously both the switching signal and the required gate power in the secondary side which ensures the full range duty ratio. The reconstruction of the original PWM signal is optimised using a simple hysteresis comparing scheme, which is the Schmitt Trigger circuit, to avoid sudden turn-on or turn-off. The experiment result shows that the Schmitt Trigger circuit could effectively avoid the sudden turn-on or turn-off but it might have some negative effect on the accuracy of duty circle. Finally, the feasibility of the gate driver is demonstrated with the PGA26E19BA GaN device with optimised final power stage