An effective method for the determination of the locking range of an injection-locked frequency divider

The paper proposes a methodology for the determination of the locking range of an Injection-Locked Frequency Divider. The technique involves the use of the Warped Multi-time scale model and is applicable to oscillators in general. The ability to determine, in an efficient manner, the locking ranges of Injection Locked Frequency Dividers is of great importance to design engineers as ILFDs are suitable for lower-power wireless applications

Evaluation of crystal oscillators and frequency dividers for high temperature operation

Active and passive components of crystal oscillators and frequency dividers were tested to determine their performance at temperatures from 300 C to 350 C. The properties of GaAs JFETs were determined and their performance compared with that of silicon devices. Techniques for constructing breadboard circuits were assessed for operation in this temperature range. A Pierce oscillator and a multivibrator (Colorado crystal) oscillator were constructed and tested. Device failures are discussed

Integrated Circuits Based on 300 GHz fT Metamorphic HEMT Technology for Millimeter-Wave and Mixed-Signal Applications

Advanced circuits based on metamorphic HEMT (MHEMT)technologies on 4 ”GaAs substrates for both millimeter-wave,and mixed- signal applications are presented.Extrinsic cut-off frequencies of ft =293 GHz and fmax =337 GHz were achieved for a 70 nm gate length metamorphic HEMT echnology.The MMIC process obtains high yield on transistor and circuit level.Single-stage low-noise amplifiers demonstrate a small signal gain of 13 dB and a noise figure of 2.8 dB at 94 GHz.An amplifier MMIC developed for D-Band operation features a gain of 15 dB at 160 GHz.The achieved results are comparable to state- of-the-art InP-based HEMT technologies.In order to realize 80 Gbit/s digital circuits,a process with 100 nm gate length enhancement type HEMTs with a transit frequency of 200 GHz is used.Three metalization layers are available for interconnects.The parasitic capacitance of the interconnects is kept low by using BCB and plated air bridge technology.Based on this process,static and dynamic frequency dividers achieve a maximu toggle frequency of 70 GHz and 108 GHz,respectively

Construction and research of reverse frequency dividers

In the work, the reversible schemes of frequency dividers are constructed based on JK triggers are offered. It is proved that reversible frequency dividers work with insignificant differences in forward and reverse inclusions. When studying the frequency divider with direct inclusion, it was found that its real frequency differs from the calculated by 1.87%. And at return inclusion frequency dividers from are calculated on 2,17%. In general, such a relative error cannot be caused by the inaccuracy of the marker placement in the Multisim virtual oscilloscope. Such reversible frequency dividers can be used in unidirectional automated systems to build neural networks

A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies. The benefit is that the proposed SPLL has the advantages of both fractional-N phase-locked loop (FN-PLL) and SPLL, such as the faster frequency switching, a smaller phase jump and a larger loop gain. Since the frequency divider can be omitted in SPLL, the associated phase noise, power and hardware consumption can be ignored. Also, the design work is simplified, since the complex multi-phase frequency divider is not needed in the proposed fractional-N sampling phase-locked loop (FN-SPLL)

A new method for the determination of the locking range of oscillators

A time-domain method for the determination of the injection-locking range of oscillators is presented. The method involves three time dimensions: the first and the second are warped time scales used for the free-running frequency and the external excitation, respectively and the third is to account for slow transients to reach a steady-state regime. The locking range is determined by tuning the frequency of the external excitation until the oscillator locks. The locking condition is determined by analyzing the Jacobian matrix of the system. The method is advantageous in that the computational effort is independent of the presence of widely separated time constants in the oscillator. Numerical results for a Van Der Pol oscillator are presented