Analog MAP decoder for (8, 4) hamming code in subthreshold CMOS

Journal ArticleAn all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s

CMOS analog map decoder for (8,4) hamming code

Journal ArticleAbstract-Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as Turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5- m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm2, and typical power consumption is 1 mW at 1 Mb/s

Analog MAP decoder for (8, 4) hamming code in subthreshold CMOS

Journal ArticleAbstract - An all-MOS analog tail-biting MAP decoder is presented for an (8,4) Hamming code. The decoder implements a probability propagation algorithm using subthreshold CMOS networks. Physical results verify the expected behavior of the decoderand demonstrate robustness of analog decoding circuits

Analog decoding of product codes

Journal ArticleAbstract - A method is presented for analog softdecision decoding of block product codes (block turbo codes). Extrinsic information is exchanged as analog signals between component row and column decoders. The component MAP decoders use low-power analog computation in subthreshold CMOS circuits to implement the sum-product algorithm. An example decoder design is presented for a (16,ll)? Hamming code

Formal verification of genetic circuits

pre-printResearchers are beginning to be able to engineer synthetic genetic circuits for a range of applications in the environmental, medical, and energy domains [1]. Crucial to the success of these efforts is the development of methods and tools to verify the correctness of these designs. This verification though is complicated by the fact that genetic circuit components are inherently noisy making their behavior asynchronous, analog, and stochastic in nature [2]. Therefore, rather than definite results, researchers are often interested in the probability of the system reaching a given state within a certain amount of time. Usually, this involves simulating the system to produce some time series data and analyzing this data to discern the state probabilities. However, as the complexity of models of genetic circuits grow, it becomes more difficult for researchers to reason about the different states by looking only at time series simulation results of the models. To address this problem, techniques from the formal verification community, such as stochastic model checking, can be leveraged [3, 4]. This tutorial will introduce the basic biology concepts needed to understand genetic circuits, as well as, the modeling and analysis techniques currently being employed. Finally, it will give insight into how formal verification techniques can be applied to genetic circuits

Analog decoding of product codes

Journal ArticleA design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decoding to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules

Implementation of SBML Level 3 Support within iBioSim

This presentation gives details about our experiences when adding SBML Level 3 support to our iBioSim tool.
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An asynchronous implementations of the MAXLIST algorithm

Journal ArticleABSTRACT We present an efficient asynchronous VLSI architecture for calculating running maximum or minimum values over a sliding window. Running maximums or minimums are very useful for many signal and image processing tasks. Our architecture performs the calculation using the MAXLIST algorithm. In order to take advantage of the wide delay variations due to data-dependencies and operating conditions, an asynchronous approach is taken to achieve higher performance and lower power. Simulation results demonstrate that our asynchronous architecture is significantly faster than existing and potential synchronous architectures

Level oriented formal model for asynchronous circuit verification and its efficient analysis method

Journal ArticleUsing a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits. On the other hand, in order to use such a model on large circuits, techniques to avoid the state explosion problem must be developed. This paper first introduces a level-oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification

Timed circuit verification using TEL structures

Journal ArticleAbstract-Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gate-level circuits. It also presents an algorithm based on partially ordered sets to make the state-space exploration o f TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gate-level timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance