Journal ArticleA design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decoding to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules

Myers, Chris J.

Winstead, Chris

English

The University of Utah: J. Willard Marriott Digital Library

Analog Decoding of Product Codes Chris Winstead1 , Chris Myers, Christian Schlegel, Reid Harrison University of Utah2 e-mail: lIinsteadCDeng. utah. edu Abstract - A design approach is presented for soft-decision decoding of block product codes ("block turbo codes") using analog computation with MOS devices. Application of analog decod-ing to large code sizes is also considered with the introduction of serial analog interfaces and pipeline schedules. r. INTRODUCTION Several authors have suggested use of analog circuits to implement probability propagation algorithms for soft-decision decoding [1][2], and some successful results have been presented [3][4][5]. Many soft decoding algorihtms have been shown to be special cases of probability prop-agation on graphs (e.g. the sum-product algorithm [6]). The structure of an analog decoder reflects the struc-ture of the code's graph, providing a straightforward path fr~m code design to physical implementation. These de-sign principles may be applied in the same way to product codes, allowing a natural transition from current analog decoder designs to more powerful block. turbo codes. II. FACTOR GRAPHS AND PRODUCT CODES A factor graph, as defined in [6J and [7J, represents a func-tion g = iI ·!2·h··-!N in terms ofits factors II, h, ... , IN. A factor graph contains function nodes, variable nodes, and edges. An edge exists between a function node I and a variable node x if and only if I depends on x. A-posteriori probabilities for variable nodes may be com-puted by propagating probability mass functions through the graph. Figure 1: Factor graph for trellis decoder. As an example, a factor graph for a typical trellis de-coder is shown in Figure 1. The variable nodes are rep-resented by circles. Channel observations, denoted in the IThis work was supported by NSF grant CCR-9971168. 2EE Dept, 50 S. Central Campus Dr, Rm 3280 MEB, Salt Lake City, UT 84112-9206 0-7803-7119-4/01/$10.00 ©2001 IEEE graph by Y, are passed into the decoder via the channel model, which is represented by the box labeled 'C'. If the code is systematic, then some of the transmitted symbols will be information (denoted U) and some symbols will be parity (denoted X). Each solid black box is a function node, and represents a trellis section. As indicated by the arrows in Figure 1, messages are passed throughout the network. Each directed edge transmits a probability mass function. A message passed on an edge to or from a binary variable x will thus be a vector containing two values, a conditional probability for x = 0 and a conditional probability for x = 1. The messages passed between trellis blocks will carry as many values as there are states in that trellis section, and so on. The algorithm which results from this message passing is equivalent to a BCJR decoder [8]. A block product code encodes the same information in two dimensions, as indicated in Figure 2. Systematic component block codes are used to separately encode the rows and the columns, thus adding separate blocks of row parity checks and column parity checks. row code ~ "0 Information 0 u Block Q S ~. ,E U \ ~ Parity Symbol s Figure 2: Product codeword structure. Graphs for the row and column codes may be indi-vidually designed as trellis codes, or Tanner graphs, or some other systematic factor graph structure. Prod-uct codes have been considered in terms of iterative de-coding in which information is exchanged between sep-arate row and column component decoders [9]. A fac-tor graph design would instead combine the component graphs into one large product-code graph. Application of the sum-product algorithm then provides concurrent decoding throughout a single graph. The factor graph of a product code can be obtained by introducing the "equal gate," a function node which indi-cates equality among the variables to which it connects. Because the component codes share information symbols, they may be connected through equal gates at any node 131 which is common to the two decoders (parity nodes re-main unaffected). This connection is illustrated in Figure 3. Channel observations are input to the decoder at vari-able node Y and passed through the equal gate to the component graphs. The overall decoder output arrives at the variable node U. row decoder •• "0"·· Figure 3: Connecting shared nodes through an equal gate. Suitable designs have been implemented for analog BCJR-style component decoders [3][4][5]. Sum-product implementation of equal gates is simple, as discussed in [10]. The equal gate propagates probabilities on a given edge by transmitting along that edge the product of mes-sages received on each other edge. Message passing in one direction through a binary equal gate is illustrated in Fig-ure 4. Following the CMOS current-mode design method of [1], one direction of message passing is implemented by the analog circuit of Figure 5. A separate propagation circuit must be built for each edge connected to the equal gate. Figure 4: Message passing in one direction. x,(0) ==---_-.l..----.J ~~::: '--____ --= x/OJ ~~---"= "0(1) Figure 5: Analog implementation of equal gate in one direction. The factor graph of Figure 3 illustrates the ease with which recent analog decoder designs may be used to build more substantial product decoders. The resulting analog product decoder replaces iterative decoding with continuous-time processing. III. INTERFACING FOR LARGER CODES Fully analog decoders have thus far only been imple-mented for small codes where inputs may be provided in parallel. A realistic design must accomodate serial chan-nel information. Serial-to-parallel conversion of analog data requires a sample-and-hold (SjR) circuit which can accurately hold an analog signal for the total time needed to decode. Leakage currents cause stored voltages to decay in or-dinary SjR circuits. Storage duration may be improved by encoding signals differentially. When used for probability propagation, analog circuits provide a natural duality for message encoding: currents may encode probabilities while differential voltages en-code log-likelihood ratios in the same circuits. The circuit of Figure 6 uses two SjR cicruits to store one differential voltage. If the two storage cells are well-matched, then their stored voltages decay at roughly the same rate. The differential voltage remains unaffected. This circuit may be used as an effective buffer for log-likelihood ratios en-coded as differential voltages. +~~+ LlV Ileak I I V In Ll out Figure 6: Differential S(H circuit. Differential S jR circuits may be used to store a stream of analog signals which are then provided simultaneously, in parallel, to the decoder. A new block of inputs may then be collected while the decoder converges to a so-lution for the previous block (a "pipeline" schedule for analog data). The signal stored in the differential SjR circuit must not fall below levels needed to bias the gates of MOS load transistors. Limitations must thus be placed on the amount of common-mode voltage decay which may be tolerated by a real circuit. In the pipelined interface, soft channel information for a single bit is provided to an array of differential SjR cir-cuits every Ts seconds. The information for each arriving bit is stored in the array until the entire block of length N is received. All of the stored analog values are then provided to an analog decoder in parallel. We assume that a minimum-length transistor pass gate is used as the switch to the SIR circuit, and that the pass gate has resistance Ron when the switch is on. A leakage 132 current I 1eak flows through the pass gate when the switch is off. To ensure that the capacitor C has adequate time to store its signal, we may place a restriction on the time-constant r = Ron C = ~. The total voltage loss .6. V in the time NTs is given by The leakage current is proportional to transistor width: I1eak = kl W. The switch's on-resistance is inversely pro-portional to the width of the same transistor: Ron = k2W-l . .6. V may therefore be expressed as where kl and k2 are constants of the process, and N is the number of bits we wish to store. This result only holds for achievable time-constants, which are limited by process design rules. A conservative CMOS design should permit sampling in the range of 1 to 10 MHz, and have the capacity to store soft information for tens of thousands of bits with negligible common-mode voltage loss. IV. IMPLEMENTATION If trellis-style graphs are used to represent the row and column codes, a tilable analog module design emerges. Figure 7 shows a module which consists of two analog trellis decoder sections (the solid black boxes), an equal gate, a differential SjH, and an output comparator. The comparator converts the product decoder's output to a final digital value. Channel Input Figure 7: Tilable analog module for a product decoder. The module of Figure 7 may be replicated and tiled to build the complete product decoder. The trellis decoder sections in each instance must be modified to reflect their code position. The result is a simple modular design, as depicted in Figure 8. The double-boxes represent sys-tematic modules, and the single boxes represent parity sections from the original trellis decoders. @ @ ...... --tr-O o @ ..... --tr-O Figure 8: Modular product decoder design. V. CONCLUSIONS Analog decoding of product codes is conceptually a small step beyond previously implemented analog block de-coders. Physically producing such a decoder requires mass storage of analog information within the decoder cir-cuit. The differential sample-and-hold circuit is a promis-ing solution to this problem. It has shown that, allowing basic design restrictions, the amount of analog informa-tion which can be stored in the circuit is a: constant of the fabrication process. Current CMOS processes appear to be generous in this regard. REFERENCES [1] H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tark6y, "Probability propagation and decoding in analog VLSI," IEEE Trans. on Information Theory, vol. 47, no. 2, pp. 837-843, February 200l. [2] J. Hagenauer, M. M6rz, E. Offer, "A circuit-based interpreta-tion of analog MAP decoding with binary trellises," Proc. 3rd ITC Conference Source and Channel Coding, Munchen, pp. 175-180, January 2000. [3] 1. Lustenberger, M. Helfenstein, H.-A. Loeliger, F. Tark6y, and G. S. Moschytz, "All-Analog decoder for a binary (18,9,5) tail-biting trellis code," Proc. European Solid-State Circuits Con-ference, pp. 362-365, Duisburg, September 1999. [4] M. Morz, T. Gabara, R. Yan, and J. Hagenauer, "An analog .25tLm BiCMOS tailbiting MAP decoder," IEEE Proc. Interna-tional Solid-State Circuits Conference, pp. 356-357, San Fran-cisco, February 2000. [5] C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, C. Schlegel, "Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS," Advanced Research in VLSI Conference, pp. 132-147, Salt Lake City, March 200l. [6] F. Kschischang, B. Frey, H.-A. Loeliger, "Factor graphs and the Sum-Product Algorithm," IEEE Trans. on Information The-ory, vol. 47, no.2, pp. 498-519, February 200l. [7] G. D. Forney, "Codes on graphs: normal realizations," IEEE Trans. on Information Theory, vol. 47, no. 2, February 200l. [8] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, "Optimal de-coding of linear codes for minimizing symbol error rate," IEEE Trans. Inform. Theory, vol. IT-20, pp. 284-287, March 1974. [9] J. Hagenauer, E. Offer, 1. Papke, "Iterative decoding of binary block and convolutional codes," IEEE Trans. on Information Theory, vol. 42, no. 2, pp. 429-445, March, 1996. [10] F. Lustenberger, On the design of analog VLSI iterative de-coders, Ph.D. Thesis, Swiss Federal Institute of Technology, Zurich, 2000. 133 

Analog decoding of product codes

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Analog decoding of product codes

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