Journal ArticleAbstract - An all-MOS analog tail-biting MAP decoder  is presented for an (8,4) Hamming code. The decoder implements a probability propagation algorithm using subthreshold CMOS networks. Physical results verify the expected behavior of the decoderand demonstrate robustness of analog decoding circuits

Myers, Chris J.

Winstead, Chris

English

The University of Utah: J. Willard Marriott Digital Library

Analog MAP Decoder for (8, 4) Hamn1.ing Code In Subthreshold CMOS Chris Winstead l , Jie Dai, Scott Little, Chris Myers, Christian Schlegel University of Utah2 e-mail: winstead@eng. utah. edu Abstract - An all-MOS analog tail-biting MAP de-coder is presented for an (8,4) Hamming code. The decoder implements a probability propagation algo-rithm using subthreshold CMOS networks. Physical results verify the expected behavior of the decoder and demonstrate robustness of analog decoding cir-cuits. The authors of [1) present a class of analog VLSI circuits which can be used to implement a general probability prop-agation algorithm for soft-decision decoding. The proposed circuits can be implemented using either bipolar transistors or weak-inversion (subthreshold) MOS devices. Researchers have implemented analog decoders in BiCMOS [2)[3). MOS transistors scale to smaller sizes than bipolar, and they may be fabricated using more common digital processes. The analog Hamming decoder was fabricated in an AMI .5f.J,m digital process, and verifies that analog decoding can be per-formed using only MOS devices. Simulation and performance verification for large analog decoder networks cannot be carried out using SPICE. An in-termediate model has been produced using VHDL which ac-counts for the physical behavior of the analog cells. This model allows prediction of the behavior of analog networks, and is used to produce the performance curves of Fig. 1. Measured output of the decoder circuit is shown in Fig. 2. The results of Fig. 2 are obtained by switching between two input patterns at 2MHz. The decoder uses 3.8 mW of power, most of which is thought to be consumed in the interfaces. BiCMOS analog decoders are expected to be faster because MOS circuits are limited to weak-inversion (device currents below ~100nA). Devices whose currents exceed this range are said to operate in strong inversion, and the assumptions made in [1) are no longer valid. The Hamming decoder nonetheless continues to function in strong inversion. Allowing device cur-rents on the order of 10f.J,A, decoding is possible up to 5 MHz (20 Mbit/s). For analog circuits, higher device currents gen-erally provide faster operation. Analog decoders are expected to degrade gracefully in re-sponse to other non-ideal circumstances such as mismatch, device noise, and process variation. Much of this flexibility arises from the parallelism inherent in the probability propa-gation algorithm. The Hamming decoder provides an excep-tional example of robustness in that it functions in spite of a layout error. Fig. 1 compares performance of an optimal MAP decoder, the analog decoder with layout error, and a corrected analog decoder. IThis work was supported by NSF grant CCR-9971168. 2EE Dept, 50 S. Central Campus Dr, Rm 3280 MEB, Salt Lake City, UT 84112-9206 3ECE Dept, 309 Dana Research Center, 360 Huntington Avenue, Boston, MA 02115 Yang-Bin Kim, Woo Jin Kim Northeastern University3 e-mail: ybk@ece. neu. edu 1(,0 1('·' 1(,-2 ~1(1-3 10-4 1(1·~ 1(1~ 0 4 SNR Fig. 1: Simulation results using VHDL model. .10-" ::R!:i\,.\ '/'~'\" '/\"'.1 /:-"\ f:" .. : \'V'-I, .. " ':t~I\/ ':;;,:'/\'"" 1~~~I,"r\"..! i~ , " ::-::-::- ;1:1 o 0.2 04 06 O.B 1 1.2 1.4 16 16 .,0" Fig;. 2: Measured response of the Hamming decoder. ACKNOWLEDGMENTS Professor Reid Harrison of the University of Utah has made many valuable contributions to our ongoing work in analog decoding. We are also indebted to Hans-Andrea Loeliger, who first introduced us to the idea of analog decoding. REFERENCES [1) H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tark6y, "Probability Propagation and Decoding in Analog VLSI," IEEE Trans. on Information Theory, pp. 837-843, February 2001. [2) F. Lustenberger, M. Helfenstein, H.-A. Loeliger, F. Tark6y, and G. S. Moschytz, "All-Analog decoder for a binary (18,9,5) tail-biting trellis code," Froc. European Solid-State Circuits Con-ference, pp. 362-365, Duisburg, September 1999. (3) M. lvIoerz, T. Gabara, R. Van, and J. Hagenauer, "An ana-log .2(iJLm BiCMOS tailbiting MAP decoder," IEEE Froc. In-ternational Solid-State Circuits Conference, pp. 356-357, San Francisco, February 2000. ----------~------------------------330 0-7803-7123-2/01/$10.00 ©2001 IEEE 

Analog MAP decoder for (8, 4) hamming code in subthreshold CMOS

Journal ArticleAn all-MOS analog implementation of a MAP decoder is presented for the (8, 4) extended Hamming code. This paper describes the design and analysis of a tail-biting trellis decoder implementation using subthreshold CMOS devices. A VLSI test chip has recently returned from fabrication, and preliminary test results indicate accurate decoding up to 20 MBit/s

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Analog MAP decoder for (8, 4) hamming code in subthreshold CMOS

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The University of Utah: J. Willard Marriott Digital Library

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