Journal ArticleAbstract - A method is presented for analog softdecision  decoding of block product codes (block turbo codes). Extrinsic information is exchanged as analog signals between component row and column decoders.  The component MAP decoders use low-power analog  computation in subthreshold CMOS circuits to  implement the sum-product algorithm. An example  decoder design is presented for a (16,ll)? Hamming  code

Myers, Chris J.

Winstead, Chris

English

Journal ArticleA method is presented for analog softdecision decoding of block product codes (block turbo codes). Extrinsic information is exchanged as analog signals between component row and column decoders. The component MAP decoders use low-power analog computation in subthreshold CMOS circuits to implement the sum-product algorithm. An example decoder design is presented for a (16,ll)? Hamming code

Harrison, Reid R.

Winstead, C.

The University of Utah: J. Willard Marriott Digital Library

Authorized licensed use limited to: The University of Utah. Downloaded on May 21,2010 at 21:13:19 UTC from IEEE Xplore.  Restrictions apply. _____________________________ ISIT 2002, Lausanne, Switzerland, June 30 - July 5,2002 Analog Decoding of Product Codes Chris Winstead! , Jie Dai, Shuhuan Yu, Reid Harrison, Chris Myers, Christian Schlegel University of Utah2 e-mail: winstead@eng. utah. edu Abstract - A method is presented for analog soft-decision decoding of block product codes (block turbo codes). Extrinsic information is exchanged as analog signals between component row and column decoders. The component MAP decoders use low-power ana-log computation in subthreshold CMOS circuits to implement the sum-product algorithm. An example decoder design is presented for a (16,11)2 Hamming code. Several authors have proposed analog circuits for soft de-coding [1,2]' and have produced designs which apply the con-cept to simple codes [3,4]. Suggestions have also been made to extend analog decoding to larger turbo-style codes. We propose to apply the analog approach to block product codes. Analog decoder designs for block codes are well established, and can be used as component decoders in larger designs. As described in [5], a block product code has a two-dimensional structure. Information is encoded in rows and columns, creating sets of row and column parity checks, and a block of checks-on-checks. Soft-in/soft-out component de-coders can be used to decode the rows and columns individ-ually. Extrinsic information produced by the row decoders is forwarded to the column decoders, and so on, producing an iterative decoding arrangement. An alternative algorithm is derived from the product code's factor graph. Each bit is shared between a row code and a column code. The two component factor graphs may be joined by an "equal node," which indicates equality among its edges, as shown in Figure 1. The entire structure is then decoded by message passing under the sum-product algorithm [6]. The node labeled 'y' in Figure 1 is a channel observation, 'u' is the coded bit (a place-holder in this graph), and 'c' represents the channel model. Existing analog decoder designs are easily connected through a circuit implementation of the equal node. Figure 2 presents an example current-mode subthreshold CMOS de-sign for an equal node based on the methodology of [1]. This circuit can be used to interconnect other current-mode sum-product circuits. Implementations of equal-node and other basic sum-product analog cicuits are detailed in [7]. A complete product decoder circuit is built from an array of component row and column decoders with an equal node circuit at each bit position. Because the equal-node connec-tions are all local, the resulting circuit layouts are regular and compact. An example design for a (16,n? Hamming decoder has about 51,000 transistors and has a simulated power con-sumption of 1mW, at a throughput of 1Mbit/s. In addition to their simple decoder structure, product codes have a well understood code structure compared to other turbo-style codes. This allows use of importance sampling IThis work was supported by NSF Grant CCR9971168. 2ECE Dept., Rm 3280 MEB, 50 S. Central Campus Dr, Salt Lake City, UT 84112-9206. -lj.fl=.:... rowdecode~ .. o = .g y ~ u "8 . Fig. 1: Component factor graphs are connected via an equal node. Edge I Ed •• , =W Ed •• , Outpul Fig. 2: Circuit for equal node implementation techniques [8] for circuit performance verification. Under im-portance sampling, it becomes feasible to include more accu-rate analog circuit models in decoder simulations. REFERENCES [1] H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tarkiiy, "Probability propagation and decoding in analog VLSI," IEEE Trans. on Information Theory, vol. 47, no. 2, pp. 837-843, February 200!. [2] J. Hagenauer, M. Miirz, E. Offer, "A circuit-based interpreta-tion of analog MAP decoding with binary trellises," Proc. 3rd ITC Conference Source and Channel Coding, Munchen, pp. 175-180, January 2000. [3] M. Miirz, T. Gabara, R. Yan, and J. Hagenauer, "An analog .25JLm BiCMOS tailbiting MAP decoder," IEEE Proc. Interna-tional Solid-State Circuits Conference, pp. 356-357, San Fran-cisco, February 2000. [4] C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, C. Schlegel, "Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS," Int. Symp. on Information Theory, Wachington D.C., June 200l. [5] J. Hagenauer, E. Offer, L. Papke, "Iterative decoding of binary block and convolutional codes," IEEE Trans. on Information Theory, vol. 42, no. 2, pp. 429-445, March, 1996. [6] F. Kschischang, B. Frey, H.-A. Loeliger, "Factor graphs and the Sum-Product Algorithm," IEEE Trans. on Information The-ory, vol. 47, no.2, pp. 498-519, February 200l. [7] F. Lustenberger, On the design of analog VLSI iterative de-coders, Ph.D. Thesis, Swiss Federal Institute of Technology, Zurich, 2000. [8] M. Ferrari and S. Bellini, "Importance sampling simulation of concatenated block codes," Proc. lEE, vol. 147, pp. 245-251, October 2000. 230 0-7803-7501-7/02/$17.00@2002IEEE. 

Analog decoding of product codes

_____________________________ ISIT 2002, Lausanne, Switzerland, June 30 - July 5,2002 Analog Decoding of Product Codes Chris Winstead! , Jie Dai, Shuhuan Yu, Reid Harrison, Chris Myers, Christian Schlegel University of Utah2 e-mail: winstead@eng. utah. edu Abstract - A method is presented for analog soft-decision decoding of block product codes (block turbo codes). Extrinsic information is exchanged as analog signals between component row and column decoders. The component MAP decoders use low-power ana-log computation in subthreshold CMOS circuits to implement the sum-product algorithm. An example decoder design is presented for a (16,11)2 Hamming code. Several authors have proposed analog circuits for soft de-coding [1,2]' and have produced designs which apply the con-cept to simple codes [3,4]. Suggestions have also been made to extend analog decoding to larger turbo-style codes. We propose to apply the analog approach to block product codes. Analog decoder designs for block codes are well established, and can be used as component decoders in larger designs. As described in [5], a block product code has a two-dimensional structure. Information is encoded in rows and columns, creating sets of row and column parity checks, and a block of checks-on-checks. Soft-in/soft-out component de-coders can be used to decode the rows and columns individ-ually. Extrinsic information produced by the row decoders is forwarded to the column decoders, and so on, producing an iterative decoding arrangement. An alternative algorithm is derived from the product code's factor graph. Each bit is shared between a row code and a column code. The two component factor graphs may be joined by an "equal node," which indicates equality among its edges, as shown in Figure 1. The entire structure is then decoded by message passing under the sum-product algorithm [6]. The node labeled 'y' in Figure 1 is a channel observation, 'u' is the coded bit (a place-holder in this graph), and 'c' represents the channel model. Existing analog decoder designs are easily connected through a circuit implementation of the equal node. Figure 2 presents an example current-mode subthreshold CMOS de-sign for an equal node based on the methodology of [1]. This circuit can be used to interconnect other current-mode sum-product circuits. Implementations of equal-node and other basic sum-product analog cicuits are detailed in [7]. A complete product decoder circuit is built from an array of component row and column decoders with an equal node circuit at each bit position. Because the equal-node connec-tions are all local, the resulting circuit layouts are regular and compact. An example design for a (16,n? Hamming decoder has about 51,000 transistors and has a simulated power con-sumption of 1mW, at a throughput of 1Mbit/s. In addition to their simple decoder structure, product codes have a well understood code structure compared to other turbo-style codes. This allows use of importance sampling IThis work was supported by NSF Grant CCR9971168. 2ECE Dept., Rm 3280 MEB, 50 S. Central Campus Dr, Salt Lake City, UT 84112-9206. -lj.fl=.:... rowdecode~ .. o = .g y ~ u "8 . Fig. 1: Component factor graphs are connected via an equal node. Edge I Ed •• , =W Ed •• , Outpul Fig. 2: Circuit for equal node implementation techniques [8] for circuit performance verification. Under im-portance sampling, it becomes feasible to include more accu-rate analog circuit models in decoder simulations. REFERENCES [1] H.-A. Loeliger, F. Lustenberger, M. Helfenstein, and F. Tarkiiy, "Probability propagation and decoding in analog VLSI," IEEE Trans. on Information Theory, vol. 47, no. 2, pp. 837-843, February 200!. [2] J. Hagenauer, M. Miirz, E. Offer, "A circuit-based interpreta-tion of analog MAP decoding with binary trellises," Proc. 3rd ITC Conference Source and Channel Coding, Munchen, pp. 175-180, January 2000. [3] M. Miirz, T. Gabara, R. Yan, and J. Hagenauer, "An analog .25JLm BiCMOS tailbiting MAP decoder," IEEE Proc. Interna-tional Solid-State Circuits Conference, pp. 356-357, San Fran-cisco, February 2000. [4] C. Winstead, J. Dai, W. J. Kim, S. Little, Y.-B. Kim, C. Myers, C. Schlegel, "Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS," Int. Symp. on Information Theory, Wachington D.C., June 200l. [5] J. Hagenauer, E. Offer, L. Papke, "Iterative decoding of binary block and convolutional codes," IEEE Trans. on Information Theory, vol. 42, no. 2, pp. 429-445, March, 1996. [6] F. Kschischang, B. Frey, H.-A. Loeliger, "Factor graphs and the Sum-Product Algorithm," IEEE Trans. on Information The-ory, vol. 47, no.2, pp. 498-519, February 200l. [7] F. Lustenberger, On the design of analog VLSI iterative de-coders, Ph.D. Thesis, Swiss Federal Institute of Technology, Zurich, 2000. [8] M. Ferrari and S. Bellini, "Importance sampling simulation of concatenated block codes," Proc. lEE, vol. 147, pp. 245-251, October 2000. 230 0-7803-7501-7/02/$17.00@2002IEEE. 

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Analog decoding of product codes

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The University of Utah: J. Willard Marriott Digital Library

The University of Utah: J. Willard Marriott Digital Library