49 research outputs found

    Viable 3C-SiC-on-Si MOSFET design disrupting current Material Technology Limitations

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    The cubic polytype (3C-) of Silicon Carbide (SiC) is an emerging semiconductor technology for power devices. The featured isotropic material properties along with the Wide Band Gap (WBG) characteristics make it an excellent choice for power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Nonetheless, material related limitations originate from the advantageous fact that 3C-SiC can be grown on Silicon (Si) wafers. One of these major limitations is an almost negligible activation of the p-type dopants after ion implantation because the annealing has to take place at relatively low temperatures. In this paper, a novel process flow for a vertical 3C-SiC-on-Si MOSFET is presented to overcome the difficulties that currently exist in obtaining a p-body region through implantation. The proposed design has been accurately simulated with Technology Computer Aided Design (TCAD) process and device software and a comparison is performed with the conventional SiC MOSFET design. The simulated output characteristics demonstrated a reduced on-resistance and at the same time it is shown that the blocking capability can be maintained to the same level. The promising performance of the novel design discussed in this paper is potentially the solution needed and a huge step towards the realisation of 3C-SiC-on-Si MOSFETs with commercially grated characteristics

    On the robustness of ultra-high voltage 4H-SiC IGBTs with an optimized retrograde p-well

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    The robustness of ultra-high voltage (>10kV) SiC IGBTs comprising of an optimized retrograde p-well is investigated. Under extensive TCAD simulations, we show that in addition to offering a robust control on threshold voltage and eliminating punch-through, the retrograde is highly effective in terms of reducing the stress on the gate oxide of ultra-high voltage SiC IGBTs. We show that a 10 kV SiC IGBT comprising of the retrograde p-well exhibits a much-reduced peak electric field in the gate oxide when compared with the counterpart comprising of a conventional p-well. Using an optimized retrograde p-well with depth as shallow as 1 μm, the peak electric field in the gate oxide of a 10kV rated SiC IGBT can be reduced to below 2 MV.cm -1 , a prerequisite to achieve a high-degree of reliability in high-voltage power devices. We therefore propose that the retrograde p-well is highly promising for the development of>10kV SiC IGBTs

    Optimal edge termination for high oxide reliability aiming 10kV SiC n-IGBTs

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    The edge termination design strongly affects the ability of a power device to support the desired voltage and its reliable operation. In this paper we present three appropriate termination designs for 10kV n-IGBTs which achieve the desired blocking requirement without the need for deep and expensive implantations. Thus, they improve the ability to fabricate, minimise the cost and reduce the lattice damage due to the high implantation energy. The edge terminations presented are optimised both for achieving the widest immunity to dopant activation and to minimise the electric field at the oxide. Thus, they ensure the long-term reliability of the device. This work has shown that the optimum design for blocking voltage and widest dose window does not necessarily give the best design for reliability. Further, it has been shown that Hybrid Junction Termination Extension structure with Space Modulated Floating Field Rings can give the best result of very high termination efficiency, as high as 99%, the widest doping variation immunity and the lowest electric field in the oxide

    Physical parameterisation of 3C-Silicon Carbide (SiC) with scope to evaluate the suitability of the material for power diodes as an alternative to 4H-SiC

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    Major recent developments in growth expertise related to the cubic polytype of Silicon Carbide, the 3C-SiC, coupled with its remarkable physical properties and the low fabrication cost, suggest that within the next five years, 3C-SiC devices can become a commercial reality. It is therefore important to develop Finite Element Method (FEM) techniques and models for accurate device simulation. Furthermore, it is also needed to perform an exhaustive simulation investigation with scope to identify which family of devices, which voltage class and for which applications this polytype is suited. In this paper, we present a complete set of physical models and material parameters for bulk 3C-SiC aiming Technology Computer Aided Design (TCAD) tools. These are compared with those of 4H-SiC, the most well developed polytype of SiC. Thereafter, the newly developed material parameters are used to assess 3C- and 4H-SiC vertical power diodes, P-i-N and Schottky Barrier Diodes (SBDs), to create trade-off maps relating the on-state voltage drop and the blocking capability. Depending on the operation requirements imposed by the application, the developed trade-off maps set the boundary of the realm for those two polytypes. It also allows us to predict which applications will benefit from an electrically graded 3C-SiC power diodes

    On the broken rotor bar diagnosis using time-frequency analysis:'Is one spectral representation enough for the characterisation of monitored signals?'

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    © 2019 Institution of Engineering and Technology. All rights reserved. This work enhances the knowledge of the diagnostic potential of the broken bar fault in induction motors. Since a series of studies have been published over the years regarding condition monitoring and fault diagnostics of these machines, it is essential to reach a common ground on why - sometimes - different techniques render different results. In this context, an investigation is provided with regards to the optimal window that should be adopted for the implementation of a proper time-frequency analysis of the monitored signals. On this agenda, this study attempts to set lower and upper bound limits for proper windowing from the digital signal processing point of view. This is done by proposing a formula for the lower limit, which is derived according to the specific frequencies one desires to put under inspection and which are the fault-related signatures. Finally, a discussion on the upper bound is put onwards; results from finite-element simulations are examined with the discussed approach in both the transient regime and the steady state, while experimental results verify the simulations with satisfying accuracy
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