CMOS Variable Gain Low Noise Amplifier for Radio Frequency Applications

The evolution of wireless telecommunication systems is expanding in an unprecedented way and such developments have prompted many design challenges specifically for low cost and low power System-on-Chip (SoC). In order to fulfill these needs, the design challenges need to be seen from all levels of the wireless system design from architecture, circuit and the process technology. The first stage of a receiver is the radio frequency (RF) input with low noise amplifier (LNA) as the first building block. Hence, it dominates the performance of the receiver system especially in noise and sensitivity. An LNA which incorporates a variable gain stage is useful in the receiver system in order to achieve continuous gain controllability which can be used to prevent saturation in the receiver when the input signal becomes relatively large compared to the power supply. Thus, circuit solutions of current mirror, gain control loop, capacitively coupled scheme and parallel inter-stage resonance are proposed. On-chip inductors are needed in a LNA to fulfill its requirements of noise and input matching. Therefore, spiral inductors are designed, analyzed and implemented according to the specifications. The main key part of this thesis describes the designs of the variable gain LNA (VGLNA) for low power consumption, continuous gain control and high selectivity over a wide frequency band with the target applications of frequency band at 2.0, 2.4, 5.0, 5.7 and 8 GHz. The VGLNA utilizes current mirror which allows precise copying of the current independent of temperature. With an adequate biased voltage applied, continuous gain control of approximately 28 dB is achieved at low current without degrading the noise performance of the VGLNA significantly, maintaining it below 2 dB. Second approach proposes the capacitively coupled LNA which ensures that the minimum required voltage supply for this topology is only one threshold voltage and not doubled the amount though it is a cascode transistors structure. Hence with these two innovative approaches, the power dissipation of the LNA would be minimal. Continuous gain control is achieved with the gain control loop and current mirror methods. By introducing a simple gain control loop composed of a gain control transistor and a capacitor, a wide continuous gain tuning range is achieved and with the current mirror, the VGLNA has continuous controllability of the gain. A new circuit structure named parallel inter-stage resonance LNA is proposed and it offers high selectivity of gain over the 5 GHz frequency band while keeping the noise figure below 2 dB. The simulation results meet the desired specifications and the measurement results of transistors and inductors are shown to be comparable with the analytical results. Finally, it can be concluded that the VGLNA designs have shown continuous controllable gain and low noise with low power consumption, not forgetting high selectivity over a wide frequency band

Digital Signal Processor (DSP) Design Using Very Long Instruction Word (VLIW) Architecture

Programmable digital signal processors (pDSP) are microprocessors that are specialized to perform well in digital signal processing-intensive applications. A standard microprocessor can do most pDSP operations. However, the pDSP chip has better ability to perform number crunching algorithms simultaneously. The objective of this research is to design and implement a general-purpose programmable DSP (Digital Signal Processor) core. The architecture of the pDSP core must be designed in such a way that parallel processing can be carried out and computational units can be integrated into the core with ease. In order to gain most benefit from the architecture, "Field Programmable Gate Array" (FPGA) technology can be used. FPGA technology is a technology, which gives the designer high flexibility in pDSP design. In order to fulfill the requirement of pDSP, "Very Long Instruction Word" (VLIW) architecture concept is used. Using, VHDL (Very-High-Speed-Integrated-Circuit Hardware Description Language) as design tool has the advantage in optimizing the pDSP hardware requirement with ease where varying the size of units such as register files (RF), program sequencer (PS), data address generator (DAG), arithmetic logic unit (ALU), multiply-accumulator (MAC) and shifter can be done by changing the data width or bit values. This flexibility of changing the data width or bit values is suitable in VLIW architecture approach. Based on the functional verification, the designed pDSP is able to perform mathematical operations required in signal processing. The speed of the operation is dependent on the size of the datapath as well as the type of FPGA chips. It has been shown that changing the data width or bit values in the VHDL source code of the subsystem can easily change the subsystems' sizes. Thus, the time for redesign is significandy shorten. Based on the verification done on Programmable Logic Device (PLO) of MAX 7000s family, the operation can be executed in 40 MIPS (Million instructions per second). However, higher MIPS value can be achieved by using higher performance FPGAIPLO chip. Therefore, it is shown that VUW architecture concept is suitable for microprocessor architecture and the pDSP core is proven to be flexible in terms of size variation of the subsystems consequently the variation of the operation speed

An improved power consumption circuit of a 5.7 GHz variable-gain low noise amplifier (VGLNA) for RF applications

A low voltage topology that uses a capacitively coupled resonating element has been introduced using 0.18 mum CMOS technology. The topology utilizes the decoupling scheme to dc isolate circuit elements that are connected in series and share a common dc current. A 5.7 GHz variable-gain low noise amplifier (VGLNA) is presented with simulation results exhibiting a noise figure of 1.02 dB, power gain of 19.41 dB with gain tuning range of 6 dB and IIP3 of -1.11 dBm. The power consumption reported is 12.88 mW at supply of Vdd = 0.7 V for power optimization circuit. Simulation results show that the proposed VGLNA has better noise performance and improved power consumption compared to the conventional cascode VGLNA

A low power 2.4 GHz variable-gain low noise amplifier for wireless applications

A 2.4 GHz variable-gain low noise amplifier (VGLNA) intended for use in a Wide-band Code Division Multiple Access receiver was designed in 0.18 um CMOS process for low voltage and low power applications. Rivaling classical designs using voltage mode approach, this design used the current mode approach, utilizing the current mirror principle to obtain a controllable gain range from 8.26 dB to 16.95 dB with good input and output return losses. By varying the current through the widths of transistors and a bias resistor, the VGLNA was capable of exhibiting 8 dB gain tuning range without degrading the noise figure. Therefore, higher gain was possible at lower current and thus at lower power consumption. Total power consumption simulated was 4.63 mW from a 1 V supply and this gave a gain/power quotient of 3.66 dB/mW. Comparing this with available published data, it was observed that this work demonstrated a good gain tuning range and the lowest noise figure with such power consumption

Meteoric 10Be as a tracer of subglacial processes and interglacial surface exposure in Greenland

In order to test whether sediment emerging from presently glaciated areas of Greenland was exposed near or at Earth's surface during previous interglacial periods, we measured the rare isotope 10Be contained in grain coatings of sediment collected at five ice marginal sites. Such grain coatings contain meteoric 10Be (10Bemet), which forms in the atmosphere and is deposited onto Earth's surface. Samples include sediment entrained in ice, glaciofluvial sediment collected at the ice margin, and subglacial sediment extracted during hot water drilling in the ablation zone. Due to burial by ice, contemporary subglacial sediment could only have acquired substantial 10Bemet concentrations during periods in the past when the Greenland Ice Sheet was less extensive than present. The highest measured 10Bemet concentrations are comparable to those found in well-developed, long-exposed soils, suggesting subglacial preservation and glacial transport of sediment exposed during preglacial or interglacial periods. Ice-bound sediment has significantly higher 10Bemet concentrations than glaciofluvial sediment, suggesting that glaciofluvial processes are sufficiently erosive to remove tracers of previous interglacial exposures. Northern Greenland sites where ice and sediment are supplied from the ice sheet's central main dome have significantly higher 10Bemet concentrations than sites in southern Greenland, indicating greater preglacial or interglacial landscape preservation in central Greenland than in the south. Because southern Greenland has more frequent and spatially extensive periods of glacial retreat but nevertheless has less evidence of past subaerial exposure, we suggest that 10Bemet measurements in glacial sediment are primarily controlled by erosional efficiency rather than interglacial exposure length

A programmable CMOS delay line for wide delay range generation and duty-cycle adjustability

A programmable CMOS delay line circuit with microsecond delay range and adjustable duty cycle is proposed. Through circuit simulation, approximately 2µs delay range can be achieved using 10-bit counter operating at a clock frequency of 500MHz. Utilising synchronous counters instead of synchronous latches has significantly reduced the large occupied active silicon area as well as the huge power consumption. The generated coarse time delay has shown excellent linearity and immunity to PVT variations. The proposed CMOS delay line is designed using a standard 0.13µm Silterra CMOS technology. The active layout area is (101 x 142) µm2, and the total power consumption is only 0.1 µW

IMPROVED SPEED LOW POWER AND LOW VOLTAGE SRAM DESIGN FOR LDPC APPLICATION CIRCUITS

The design of SRAM has evolved to suffice the need of the industry in terms of speed, power dissipation and other parameters. This paper proposed a SRAM design and an attempt has been made to design circuits using dynamic logic and pass transistor logic to obtain better performance in terms of speed, power dissipation and throughput. The dynamic logic would maintain voltage degradation by using the PMOS and NMOS transistor just as the CMOS logic, even though the design cell uses majority NMOS transistors. The proposed circuits are simulated using BSIM for different CMOS feature sizes of 70 nm, 90 nm, 120 nm and 180 nm. The results obtained have been analysed and shows that the proposed circuit of 8T performs much better as compared to other circuit configurations. There is significant improvement in power dissipation by 99.64 %, delay by 99.9 %, throughput of 490 Mbps and power delay product of 99.96 %

Figure-of-Merits (FOM) for Direct Current TENG (Triboelectric Nanogenerator): Structural vs Dimensionless

This review paper provides a detailed overview of figure-of-merits (FOM) of Direct Current triboelectric nanogenerators (DC-TENGs). TENG represent a potentially ground-breaking technology for extracting mechanical energy from the environment. The FOM is a critical parameter that determines the efficiency of the energy conversion. This paper discusses the various working modes of DC-TENGs and also the research done to maximize output charge density. The review looks at recent different FOMs that could be formulated to improve the analysis of the performance and efficiency of TENGs more accurately. Finally, the paper concludes with a comparison between two different types of FOMs namely structural FOMs and dimensionless FOMs. It provides a valuable resource for researchers working in the field of TENGs and it sheds light on the key factors that influence the FOM of DC-TENGs. This enables the development of more efficient energy harvesting devices

Cascode current mirror for a variable gain stage in a 1.8 GHz low noise amplifier (LNA)

A high frequency CMOS variable gain low noise amplifier (VGLNA) constructed based on an inductive source degenerated LNA and a cascode current mirror is proposed. The 'variable' concept is to prevent the unwanted saturation phenomenon due to large input signal. A cascode current mirror cell which consumes minimal voltage headroom without sacrificing the accuracy of the circuit is proposed in the circuit. With a 0.18 m CMOS technology, this technique is applied on a VGLNA operating at 1.8 GHz for GSM band application. The simulation results reveal that the maximum gain is 17.29 dB with gain tuning range of 9.56 dB. The noise figure (NF)is less than 0.92 dB with the power consumption of 9.34 mW at power supply of 1.8 V. Comparison with several same operating frequency LNA circuits published show that this work demonstrated among the lowest NF and highest IIP3 with compromise on the gain

Preservation of a Preglacial Landscape Under the Center of the Greenland Ice Sheet

Continental ice sheets typically sculpt landscapes via erosion; under certain conditions, ancient landscapes can be preserved beneath ice and can survive extensive and repeated glaciation. We used concentrations of atmospherically produced cosmogenic beryllium-10, carbon, and nitrogen to show that ancient soil has been preserved in basal ice for millions of years at the center of the ice sheet at Summit, Greenland. This finding suggests ice sheet stability through the Pleistocene (i.e., the past 2.7 million years). The preservation of this soil implies that the ice has been non-erosive and frozen to the bed for much of that time, that there was no substantial exposure of central Greenland once the ice sheet became fully established, and that preglacial landscapes can remain preserved for long periods under continental ice sheet