TEGESED, a tool for efficient technological and geometrical characterization of semiconductor devices

Characterization of semiconductor devices in terms of their technological and geometrical parameters is de- scribed in this paper. This characterization is generated by a software tool composed of the SPICE-PAC simula- tion package and the symbolic simulator SYBILIN. The paper discusses the general structure of the program, its principle of operation, some implementation details, and its computational efficiency. A characterization of Heterojunction Bipolar Transistor (HBT) for microwave applications is used as an illustration

Symbolic analysis in parameter extraction, its implementation and performance

An interface between a symbolic analysis tool and a SPICE–like circuit simulation pack- age has been developed in order to integrate numerical and symbolic circuit analyses. In effect, both numerical and symbolic analyses use the same internal representation of circuits which makes the two approaches truly complementary. This integrated simulation capabil- ity is used in simulation–based parameter extraction where all ac small-signal parameters are fitted through the symbolic analysis rather than numerical one, significantly reducing the execution time of the extraction process

FIT–2, A SIMULATION–BASED PARAMETER EXTRACTION PROGRAM

Accurate and reliable simulation of circuit behavior cannot be obtained without ade- quate device models. FIT–2 is an interactive program for extraction of transistor parameters for SPICE–like circuit simulators. It is based on a circuit simulator rather than an explicit set of model equations. Basic advantages of the proposed approach include: (1) explicit model equations need not be known as they are provided by the circuit simulation tool used, (2) fitting can be performed not only for single devices but for functional blocks or whole circuits as well, and (3) the same extractor can be used for a variety of devices and/or device models. Several optimization methods are built into the program to provide robust as well as efficient fitting of device characteristics. Flexibility of the approach is obtained by specification of extraction details in the data sets rather than the extraction procedure. Parameter extraction for heterojunction bipolar transistors (HBT) is used as an illustration of FIT-2 capabilities. The effects of optimization methods on extraction performance are presented. Several directions for further research are identified

Improving performance of parameter extractors through symbolic simulation

In parameter extraction programs, the performance of repeated analyses of linear (or linearized) circuits can be significantly improved by representing the dependence of circuit responses on some parameters in a symbolic form. This symbolic form can then be evaluated very efficiently for different sets of parameter values. An integrated numerical-symbolic parameter extraction program, called FIT-S, has been developed in which all linear circuit analyses can be performed using a symbolic or numerical approach. A comparisons of execution times is presented for extraction of a submicron HEMT's parameters

Distributed transmission lines and time-domain analysis in SPICE-like circuit simulators

Several problems arising in the SPICE implementation of the time-domain analysis of circuits with distributed transmission lines are indicated, and it is shown that some simple modifications of the original handling of transmission lines can significantly reduce both memory requirements and CPU time needed for this analysis. The modifications allow to `trade' simulation time for accuracy of results. In effect, results more accurate than the original SPICE ones can be obtained with much smaller computational effort. An example of microwave oscillator is used as an illustration of proposed improvements

Technological and geometrical optimisation of InP HBT driver circuit

The design of high speed circuits and optimization in function of technological and geometrical parameters are presented. MUX-driver design and optimization for 40 Gb/s ETDM transmission illustrate the proposed approach. The impact of collector thickness (WC) on driver performances is evaluated and assessed by circuit fabrication and measurements. 40 Gb/s electrical measurements of the realized MUX-driver module are presented