The design of high speed circuits and optimization in function of technological and geometrical parameters are presented. MUX-driver design and optimization for 40 Gb/s ETDM transmission illustrate the proposed approach. The impact of collector thickness (WC) on driver performances is evaluated and assessed by circuit fabrication and measurements. 40 Gb/s electrical measurements of the realized MUX-driver module are presented

André, P.

Benchimol, J.L.

Blayac, S.

Kauffmann, N.

Konczykowska, A.

Riet, M.

English

AMS Acta - Alm@DL - Università di Bologna

TECHNOLOGICAL AND GEOMETRICAL OPTIMISATION
OF InP HBT DRIVER CIRCUIT
N. Kauffmann, S. Blayac, P. André, M. Riet, J.-L. Benchimol, A. Konczykowska
OPTO+, Groupement d’Intérêt Economique
France Telecom R&D
Route de Nozay, F-91461 Marcoussis Cedex
agnieszka.konczykowska@optoplus.fr
ABSTRACT
The design of high speed circuits and optimization in function of technological and
geometrical parameters are presented. MUX-driver design and optimization for 40 Gb/s
ETDM transmission illustrate the proposed approach. The impact of collector thickness (WC)
on driver performances is evaluated and assessed by circuit fabrication and measurements.
40 Gb/s electrical measurements of the realized MUX-driver module are presented.
INTRODUCTION
The important increase of communication services and particularly the data-transmission
traffic needs to be supported by the development of adequate communication networks. High
speed electronic circuits can be successfully used in high bitrate Time Division Multiplexing
(TDM ) transmission systems [1]. The constant progresses in semiconductor technology offer
new possibilities to circuit designers. Single wavelength 40 Gb/s ETDM transmission has
been demonstrated and could, in association with Dense Wavelength-Division Multiplexing
(DWDM), allow to attain Terabit/s transmission rates.
TECHNOLOGY
An InP DHBT self-aligned technology has been developed at the OPTO+ laboratory [2]. This
technology is well suited for the very high speed ICs and particularly for driver design
because of good frequency performances (Ft and Fmax of 125 GHz and 83 GHz have been
measured for Vce = 1.6 V and J = 0.8 mA/µm2) combined with high gain (> 50) and high
breakdown voltage (> 7 V). The use of a compositionally graded InGaAs base and self-
alignment explains these good dynamic performances. In this technology both the transit time
(graded base) and collector-base capacitance (collector undercutting allowed by self-
alignment) are significantly reduced. Minimum emitter length and width of the transistors is
2.2 µm × 2.2 µm. Current densities up to 1 mA/µm2 may be used without degrading the
circuit reliability. The technology also provides three metallic levels, allowing optimisation of
routing and layout symetrisation.
PREDICTIVE MODELLING
The successful design of high performance circuits must be supported by an important
modelling effort. Rapid evolution and progress in semiconductor technologies require
modelling which can answer both technology and CAD needs. In [3] we reported a realisation
of the modelling tool ACPAR2A, allowing predictive design of high performance circuits
using evolving HBT technology. The main function of ACPAR2A is to compute CAD models
using analytical formulae in function of technological and geometric parameters. ACPAR2A
has been used in a prediction-extraction scheme, serving in the first phase for device
optimisation and lately for full-custom design (transistor sizing), once the technology is
validated and predicted model verified with parameter values extracted from measurements of
realised transistors.
In the next section, we show how ACPAR2A can be used for evaluation of circuit
performances in function of technological parameters.
MUX-DRIVER CIRCUIT OPTIMISATION
The MUX-driver circuit in the above-presented InP DHBT technology has been designed for
40 Gb/s ETDM system experiments with an Electro Absorption Modulator (EAM). The
MUX-driver integrates two functions: last 2:1 multiplexing stage and EAM driver. Output
swing above 2 V is one of the circuit specifications. The difficulty of this design lays in the
combined requirements of a high bitrate and of an important output signal. One critical point
in the design of the driver circuit is the choice of the optimal current density of the transistors.
On one side, small transistors are required to satisfy high speed specifications, while an
important current is necessary to obtain a high output swing.
Among different technological and process parameters, the collector epilayer thickness (WC)
is an important one because:
• WC controls the important trade-off between the base-collector capacitance CBC and the
forward transit time τF
• WC sets the high injection level and therefore the range of operating current of the
transistor.
• WC sets the breakdown voltage BVCE
Besides, WC can be easily set in the heterostructure epitaxial growth process. A more detailed
analysis shows that a trade-off between two transistor parameters (collector transit time and
capacitance) has to be set correctly to achieve best performances not only for the device but
also for the circuit.
The transit time in function of Wc is presented in Fig. 1. In Fig. 2, the InP HBT transition
frequency (Ft) is presented for 3 different Wc. The transistor emitter size is 19.2x2.2 µm2
ensuring frequency and signal properties suitable for driver applications. The driver
architecture was discussed previously [4] and following choices were made. The driver is
composed of four stages, two differential current switches (CS) driven by emitter-followers
(EFs) for level shifting and impedance transformation. For the third stage, three EFs have to
be cascaded instead of the two used in E2CL logic, because the impedance transformation is
not very efficient at high frequencies. These EFs have to be carefully designed in order to
avoid ringing, due to their inductive, low ohmic output, combined with their capacitive input.
The layout must be carefully realised, and specially connections driven by EF stages.
In Fig. 3 and Fig. 4 we present two important aspects of the driver quality: output swing level
and the time jitter. Simulations were realised in function of the driver speed and for different
Wc values. It can be noticed that the optimal performance combining the necessary swing (>2
V) and limited time jitter can be obtained for the collector thickness Wc situated between
2500 Å and 3000 Å. In Fig. 5 eye-diagram simulations show the differences in the eye-
opening and jitter for different Wc.
The circuit was fabricated with different layers standards (Wc = 1500, 2500, 3500 Å).
Measurement results are in concordance with those predicted by simulation. Best results were
obtained for Wc = 2500 Å. In Fig. 6, the measurement of the driver module (2.2 Vpp for 40
Gb/s) is presented. The circuit was realised and used in successful optical system experiments
at 40 Gb/s transmission [4].
CONCLUSIONS AND PERSPECTIVES
In this paper we presented the MUX-driver optimisation in function of technological and
geometrical parameters. It was shown that in addition to optimisation of planar geometrical
parameters (transistor sizing) the influence of the layer structure can be evaluated and
optimised for circuit applications. The performances of the MUX-driver for 40 Gb/s operation
were simulated for different collector thickness. The predicted performances are in good
agreement with the measurements of the realised circuit.
New perspectives for driver performances are opened by continuous technology progress (InP
DHBT with 170 GHz FT and 210 GHz FMAX were reported in [5]).
This rapid technology progress assesses the need for tools, as those presented above, allowing
to rapidly evaluate the impact of technological and geometric parameters on circuit
performances.
ACKNOWLEDGEMENT
Authors would like to thank J. Godin and A. Scavennec for encouragement and fruitful
discussions and  M. Abboun and  F. Aniel for modelling work.
REFERENCES
[1] Mikio Yoneyama et al., Fully electrical 40-Gbit/s TDM system prototype and its application to 160-Gbit/s
WDM transmission, OFC’99, San Diego, CA, USA, February 99, pp. 128-13
[2] S. Blayac, M. Riet, J.L. Benchimol, M. Abboun, F. Aniel, P. Berdaguer, A.M. Duchenois, A. Konczykowska,
J. Godin, InP HBT self-aligned technology for 40 Gbit/s ICs: Fabrication and CAD geometric models,
IPRM'99, Davos, Switzerland, May 1999, pp. 483-486
[3] A. Konczykowska, S. Blayac, M. Abboun, N. Kauffmann, M. Riet, F. Aniel, Prediction-extraction modelling
scheme for design of high speed circuits, ECCTD’99, Stresa, September 99, pp. 904-907
[4] N. Kauffmann, P. André, J.R. Burie, A.M. Duchenois, M. Riet, A. Konczykowska, 44 Gb/s DHBT MUX-
driver IC for External Laser Modulation,  GAAS’99, Munich, October 99, pp. 354-357
[5]  S. Blayac, M. Riet, J.L. Benchimol, P. Berdaguer, N. Kauffmann, J. Godin, A. Scavennec, “Lateral design of
InP/InGaAs DHBTs for 40 Gbit/s ICs”, Proc. of IPRM 2000.
0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7
0,0
0,2
0,4
0,6
0,8
1,0
1,2
1,4
1,6
 Model
Measurement
TF
 (p
s)
Wc (µm)
Fig. 1   Transit time in function of Wc
0 20 40 60 80
20
40
60
80
100
120
140
160
180
 1500 A°
 2500 A°
 3500 A°
 Fit
Ft
 
(G
H
z
)
Ic (mA)
1500 Å
2500 Å
5000 Å
Fig. 2   Ft for different Wc
00,5
1
1,5
2
2,5
3
20 25 30 35 40 45 50 55 60
Bit-rate (Gb/s)
O
ut
pu
t s
w
in
g 
(V
) 
Wc=1500 A
Wc=2000 A
Wc=2500 A
Wc=3000 A
Wc=3500 A
Fig. 3   MUX-driver output swing
0
2
4
6
8
10
12
20 30 40 50 60
Bit-rate (Gb/s)
Ti
m
e 
jitt
er
 (p
s) 
Wc=1500 A
Wc=2000 A
Wc=2500 A
Wc=3000 A
Wc=3500 A
Time jitter @ 40 Gb/s
02
46
8
1000 3000 5000
Wc
Ti
m
e 
 (p
s)
Fig. 4   MUX-driver time jitter
      
              45 Gb/s (1500 Å)                                        55 Gb/s (2500 Å)
              
             55 Gb/s (3000 Å)                                         55 Gb/s (3500 Å)
Fig. 5   Output signal simulation for different bitrates and different Wc
Fig. 6   MUX-Driver module measurement (40 Gb/s 2,2 Vpp)


Technological and geometrical optimisation of InP HBT driver circuit

AMS Acta

TECHNOLOGICAL AND GEOMETRICAL OPTIMISATIONOF InP HBT DRIVER CIRCUITN. Kauffmann, S. Blayac, P. André, M. Riet, J.-L. Benchimol, A. KonczykowskaOPTO+, Groupement d’Intérêt EconomiqueFrance Telecom R&DRoute de Nozay, F-91461 Marcoussis Cedexagnieszka.konczykowska@optoplus.frABSTRACTThe design of high speed circuits and optimization in function of technological andgeometrical parameters are presented. MUX-driver design and optimization for 40 Gb/sETDM transmission illustrate the proposed approach. The impact of collector thickness (WC)on driver performances is evaluated and assessed by circuit fabrication and measurements.40 Gb/s electrical measurements of the realized MUX-driver module are presented.INTRODUCTIONThe important increase of communication services and particularly the data-transmissiontraffic needs to be supported by the development of adequate communication networks. Highspeed electronic circuits can be successfully used in high bitrate Time Division Multiplexing(TDM ) transmission systems [1]. The constant progresses in semiconductor technology offernew possibilities to circuit designers. Single wavelength 40 Gb/s ETDM transmission hasbeen demonstrated and could, in association with Dense Wavelength-Division Multiplexing(DWDM), allow to attain Terabit/s transmission rates.TECHNOLOGYAn InP DHBT self-aligned technology has been developed at the OPTO+ laboratory [2]. Thistechnology is well suited for the very high speed ICs and particularly for driver designbecause of good frequency performances (Ft and Fmax of 125 GHz and 83 GHz have beenmeasured for Vce = 1.6 V and J = 0.8 mA/µm2) combined with high gain (> 50) and highbreakdown voltage (> 7 V). The use of a compositionally graded InGaAs base and self-alignment explains these good dynamic performances. In this technology both the transit time(graded base) and collector-base capacitance (collector undercutting allowed by self-alignment) are significantly reduced. Minimum emitter length and width of the transistors is2.2 µm × 2.2 µm. Current densities up to 1 mA/µm2 may be used without degrading thecircuit reliability. The technology also provides three metallic levels, allowing optimisation ofrouting and layout symetrisation.PREDICTIVE MODELLINGThe successful design of high performance circuits must be supported by an importantmodelling effort. Rapid evolution and progress in semiconductor technologies requiremodelling which can answer both technology and CAD needs. In [3] we reported a realisationof the modelling tool ACPAR2A, allowing predictive design of high performance circuitsusing evolving HBT technology. The main function of ACPAR2A is to compute CAD modelsusing analytical formulae in function of technological and geometric parameters. ACPAR2Ahas been used in a prediction-extraction scheme, serving in the first phase for deviceoptimisation and lately for full-custom design (transistor sizing), once the technology isvalidated and predicted model verified with parameter values extracted from measurements ofrealised transistors.In the next section, we show how ACPAR2A can be used for evaluation of circuitperformances in function of technological parameters.MUX-DRIVER CIRCUIT OPTIMISATIONThe MUX-driver circuit in the above-presented InP DHBT technology has been designed for40 Gb/s ETDM system experiments with an Electro Absorption Modulator (EAM). TheMUX-driver integrates two functions: last 2:1 multiplexing stage and EAM driver. Outputswing above 2 V is one of the circuit specifications. The difficulty of this design lays in thecombined requirements of a high bitrate and of an important output signal. One critical pointin the design of the driver circuit is the choice of the optimal current density of the transistors.On one side, small transistors are required to satisfy high speed specifications, while animportant current is necessary to obtain a high output swing.Among different technological and process parameters, the collector epilayer thickness (WC)is an important one because:• WC controls the important trade-off between the base-collector capacitance CBC and theforward transit time τF• WC sets the high injection level and therefore the range of operating current of thetransistor.• WC sets the breakdown voltage BVCEBesides, WC can be easily set in the heterostructure epitaxial growth process. A more detailedanalysis shows that a trade-off between two transistor parameters (collector transit time andcapacitance) has to be set correctly to achieve best performances not only for the device butalso for the circuit.The transit time in function of Wc is presented in Fig. 1. In Fig. 2, the InP HBT transitionfrequency (Ft) is presented for 3 different Wc. The transistor emitter size is 19.2x2.2 µm2ensuring frequency and signal properties suitable for driver applications. The driverarchitecture was discussed previously [4] and following choices were made. The driver iscomposed of four stages, two differential current switches (CS) driven by emitter-followers(EFs) for level shifting and impedance transformation. For the third stage, three EFs have tobe cascaded instead of the two used in E2CL logic, because the impedance transformation isnot very efficient at high frequencies. These EFs have to be carefully designed in order toavoid ringing, due to their inductive, low ohmic output, combined with their capacitive input.The layout must be carefully realised, and specially connections driven by EF stages.In Fig. 3 and Fig. 4 we present two important aspects of the driver quality: output swing leveland the time jitter. Simulations were realised in function of the driver speed and for differentWc values. It can be noticed that the optimal performance combining the necessary swing (>2V) and limited time jitter can be obtained for the collector thickness Wc situated between2500 Å and 3000 Å. In Fig. 5 eye-diagram simulations show the differences in the eye-opening and jitter for different Wc.The circuit was fabricated with different layers standards (Wc = 1500, 2500, 3500 Å).Measurement results are in concordance with those predicted by simulation. Best results wereobtained for Wc = 2500 Å. In Fig. 6, the measurement of the driver module (2.2 Vpp for 40Gb/s) is presented. The circuit was realised and used in successful optical system experimentsat 40 Gb/s transmission [4].CONCLUSIONS AND PERSPECTIVESIn this paper we presented the MUX-driver optimisation in function of technological andgeometrical parameters. It was shown that in addition to optimisation of planar geometricalparameters (transistor sizing) the influence of the layer structure can be evaluated andoptimised for circuit applications. The performances of the MUX-driver for 40 Gb/s operationwere simulated for different collector thickness. The predicted performances are in goodagreement with the measurements of the realised circuit.New perspectives for driver performances are opened by continuous technology progress (InPDHBT with 170 GHz FT and 210 GHz FMAX were reported in [5]).This rapid technology progress assesses the need for tools, as those presented above, allowingto rapidly evaluate the impact of technological and geometric parameters on circuitperformances.ACKNOWLEDGEMENTAuthors would like to thank J. Godin and A. Scavennec for encouragement and fruitfuldiscussions and  M. Abboun and  F. Aniel for modelling work.REFERENCES[1] Mikio Yoneyama et al., Fully electrical 40-Gbit/s TDM system prototype and its application to 160-Gbit/sWDM transmission, OFC’99, San Diego, CA, USA, February 99, pp. 128-13[2] S. Blayac, M. Riet, J.L. Benchimol, M. Abboun, F. Aniel, P. Berdaguer, A.M. Duchenois, A. Konczykowska,J. Godin, InP HBT self-aligned technology for 40 Gbit/s ICs: Fabrication and CAD geometric models,IPRM'99, Davos, Switzerland, May 1999, pp. 483-486[3] A. Konczykowska, S. Blayac, M. Abboun, N. Kauffmann, M. Riet, F. Aniel, Prediction-extraction modellingscheme for design of high speed circuits, ECCTD’99, Stresa, September 99, pp. 904-907[4] N. Kauffmann, P. André, J.R. Burie, A.M. Duchenois, M. Riet, A. Konczykowska, 44 Gb/s DHBT MUX-driver IC for External Laser Modulation,  GAAS’99, Munich, October 99, pp. 354-357[5]  S. Blayac, M. Riet, J.L. Benchimol, P. Berdaguer, N. Kauffmann, J. Godin, A. Scavennec, “Lateral design ofInP/InGaAs DHBTs for 40 Gbit/s ICs”, Proc. of IPRM 2000.0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,70,00,20,40,60,81,01,21,41,6 ModelMeasurementTF (ps)Wc (µm)Fig. 1   Transit time in function of Wc0 20 40 60 8020406080100120140160180 1500 A° 2500 A° 3500 A° FitFt (GHz)Ic (mA)1500 Å2500 Å5000 ÅFig. 2   Ft for different Wc00,511,522,5320 25 30 35 40 45 50 55 60Bit-rate (Gb/s)Output swing (V) Wc=1500 AWc=2000 AWc=2500 AWc=3000 AWc=3500 AFig. 3   MUX-driver output swing02468101220 30 40 50 60Bit-rate (Gb/s)Time jitter (ps) Wc=1500 AWc=2000 AWc=2500 AWc=3000 AWc=3500 ATime jitter @ 40 Gb/s024681000 3000 5000WcTime  (ps)Fig. 4   MUX-driver time jitter                    45 Gb/s (1500 Å)                                        55 Gb/s (2500 Å)                           55 Gb/s (3000 Å)                                         55 Gb/s (3500 Å)Fig. 5   Output signal simulation for different bitrates and different WcFig. 6   MUX-Driver module measurement (40 Gb/s 2,2 Vpp)

TECHNOLOGICAL AND GEOMETRICAL OPTIMISATION
OF InP HBT DRIVER CIRCUIT
N. Kauffmann, S. Blayac, P. André, M. Riet, J.-L. Benchimol, A. Konczykowska
OPTO+, Groupement d’Intérêt Economique
France Telecom R&D
Route de Nozay, F-91461 Marcoussis Cedex
agnieszka.konczykowska@optoplus.fr
ABSTRACT
The design of high speed circuits and optimization in function of technological and
geometrical parameters are presented. MUX-driver design and optimization for 40 Gb/s
ETDM transmission illustrate the proposed approach. The impact of collector thickness (WC)
on driver performances is evaluated and assessed by circuit fabrication and measurements.
40 Gb/s electrical measurements of the realized MUX-driver module are presented.
INTRODUCTION
The important increase of communication services and particularly the data-transmission
traffic needs to be supported by the development of adequate communication networks. High
speed electronic circuits can be successfully used in high bitrate Time Division Multiplexing
(TDM ) transmission systems [1]. The constant progresses in semiconductor technology offer
new possibilities to circuit designers. Single wavelength 40 Gb/s ETDM transmission has
been demonstrated and could, in association with Dense Wavelength-Division Multiplexing
(DWDM), allow to attain Terabit/s transmission rates.
TECHNOLOGY
An InP DHBT self-aligned technology has been developed at the OPTO+ laboratory [2]. This
technology is well suited for the very high speed ICs and particularly for driver design
because of good frequency performances (Ft and Fmax of 125 GHz and 83 GHz have been
measured for Vce = 1.6 V and J = 0.8 mA/µm2) combined with high gain (> 50) and high
breakdown voltage (> 7 V). The use of a compositionally graded InGaAs base and self-
alignment explains these good dynamic performances. In this technology both the transit time
(graded base) and collector-base capacitance (collector undercutting allowed by self-
alignment) are significantly reduced. Minimum emitter length and width of the transistors is
2.2 µm × 2.2 µm. Current densities up to 1 mA/µm2 may be used without degrading the
circuit reliability. The technology also provides three metallic levels, allowing optimisation of
routing and layout symetrisation.
PREDICTIVE MODELLING
The successful design of high performance circuits must be supported by an important
modelling effort. Rapid evolution and progress in semiconductor technologies require
modelling which can answer both technology and CAD needs. In [3] we reported a realisation
of the modelling tool ACPAR2A, allowing predictive design of high performance circuits
using evolving HBT technology. The main function of ACPAR2A is to compute CAD models
using analytical formulae in function of technological and geometric parameters. ACPAR2A
has been used in a prediction-extraction scheme, serving in the first phase for device
optimisation and lately for full-custom design (transistor sizing), once the technology is
validated and predicted model verified with parameter values extracted from measurements of
realised transistors.
In the next section, we show how ACPAR2A can be used for evaluation of circuit
performances in function of technological parameters.
MUX-DRIVER CIRCUIT OPTIMISATION
The MUX-driver circuit in the above-presented InP DHBT technology has been designed for
40 Gb/s ETDM system experiments with an Electro Absorption Modulator (EAM). The
MUX-driver integrates two functions: last 2:1 multiplexing stage and EAM driver. Output
swing above 2 V is one of the circuit specifications. The difficulty of this design lays in the
combined requirements of a high bitrate and of an important output signal. One critical point
in the design of the driver circuit is the choice of the optimal current density of the transistors.
On one side, small transistors are required to satisfy high speed specifications, while an
important current is necessary to obtain a high output swing.
Among different technological and process parameters, the collector epilayer thickness (WC)
is an important one because:
•  WC controls the important trade-off between the base-collector capacitance CBC and the
forward transit time τF
•  WC sets the high injection level and therefore the range of operating current of the
transistor.
•  WC sets the breakdown voltage BVCE
Besides, WC can be easily set in the heterostructure epitaxial growth process. A more detailed
analysis shows that a trade-off between two transistor parameters (collector transit time and
capacitance) has to be set correctly to achieve best performances not only for the device but
also for the circuit.
The transit time in function of Wc is presented in Fig. 1. In Fig. 2, the InP HBT transition
frequency (Ft) is presented for 3 different Wc. The transistor emitter size is 19.2x2.2 µm2
ensuring frequency and signal properties suitable for driver applications. The driver
architecture was discussed previously [4] and following choices were made. The driver is
composed of four stages, two differential current switches (CS) driven by emitter-followers
(EFs) for level shifting and impedance transformation. For the third stage, three EFs have to
be cascaded instead of the two used in E2CL logic, because the impedance transformation is
not very efficient at high frequencies. These EFs have to be carefully designed in order to
avoid ringing, due to their inductive, low ohmic output, combined with their capacitive input.
The layout must be carefully realised, and specially connections driven by EF stages.
In Fig. 3 and Fig. 4 we present two important aspects of the driver quality: output swing level
and the time jitter. Simulations were realised in function of the driver speed and for different
Wc values. It can be noticed that the optimal performance combining the necessary swing (>2
V) and limited time jitter can be obtained for the collector thickness Wc situated between
2500 Å and 3000 Å. In Fig. 5 eye-diagram simulations show the differences in the eye-
opening and jitter for different Wc.
The circuit was fabricated with different layers standards (Wc = 1500, 2500, 3500 Å).
Measurement results are in concordance with those predicted by simulation. Best results were
obtained for Wc = 2500 Å. In Fig. 6, the measurement of the driver module (2.2 Vpp for 40
Gb/s) is presented. The circuit was realised and used in successful optical system experiments
at 40 Gb/s transmission [4].
CONCLUSIONS AND PERSPECTIVES
In this paper we presented the MUX-driver optimisation in function of technological and
geometrical parameters. It was shown that in addition to optimisation of planar geometrical
parameters (transistor sizing) the influence of the layer structure can be evaluated and
optimised for circuit applications. The performances of the MUX-driver for 40 Gb/s operation
were simulated for different collector thickness. The predicted performances are in good
agreement with the measurements of the realised circuit.
New perspectives for driver performances are opened by continuous technology progress (InP
DHBT with 170 GHz FT and 210 GHz FMAX were reported in [5]).
This rapid technology progress assesses the need for tools, as those presented above, allowing
to rapidly evaluate the impact of technological and geometric parameters on circuit
performances.
ACKNOWLEDGEMENT
Authors would like to thank J. Godin and A. Scavennec for encouragement and fruitful
discussions and  M. Abboun and  F. Aniel for modelling work.
REFERENCES
[1] Mikio Yoneyama et al., Fully electrical 40-Gbit/s TDM system prototype and its application to 160-Gbit/s
WDM transmission, OFC’99, San Diego, CA, USA, February 99, pp. 128-13
[2] S. Blayac, M. Riet, J.L. Benchimol, M. Abboun, F. Aniel, P. Berdaguer, A.M. Duchenois, A. Konczykowska,
J. Godin, InP HBT self-aligned technology for 40 Gbit/s ICs: Fabrication and CAD geometric models,
IPRM'99, Davos, Switzerland, May 1999, pp. 483-486
[3] A. Konczykowska, S. Blayac, M. Abboun, N. Kauffmann, M. Riet, F. Aniel, Prediction-extraction modelling
scheme for design of high speed circuits, ECCTD’99, Stresa, September 99, pp. 904-907
[4] N. Kauffmann, P. André, J.R. Burie, A.M. Duchenois, M. Riet, A. Konczykowska, 44 Gb/s DHBT MUX-
driver IC for External Laser Modulation,  GAAS’99, Munich, October 99, pp. 354-357
[5]  S. Blayac, M. Riet, J.L. Benchimol, P. Berdaguer, N. Kauffmann, J. Godin, A. Scavennec, “Lateral design of
InP/InGaAs DHBTs for 40 Gbit/s ICs”, Proc. of IPRM 2000.
0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7
0,0
0,2
0,4
0,6
0,8
1,0
1,2
1,4
1,6
 Model
Measurement
TF
 (
ps
)
Wc (µm)
Fig. 1   Transit time in function of Wc
0 20 40 60 80
20
40
60
80
100
120
140
160
180
 1500 A°
 2500 A°
 3500 A°
 Fit
F
t 
(G
H
z)
Ic (mA)
1500 Å
2500 Å
5000 Å
Fig. 2   Ft for different Wc
0
0,5
1
1,5
2
2,5
3
20 25 30 35 40 45 50 55 60
Bit-rate (Gb/s)
O
u
tp
u
t 
sw
in
g
 (
V
) 
Wc=1500 A
Wc=2000 A
Wc=2500 A
Wc=3000 A
Wc=3500 A
Fig. 3   MUX-driver output swing
0
2
4
6
8
10
12
20 30 40 50 60
Bit-rate (Gb/s)
T
im
e 
jit
te
r 
(p
s)
 
Wc=1500 A
Wc=2000 A
Wc=2500 A
Wc=3000 A
Wc=3500 A
Time jitter @ 40 Gb/s
0
2
4
6
8
1000 3000 5000
Wc
T
im
e 
 (
ps
)
Fig. 4   MUX-driver time jitter
      
              45 Gb/s (1500 Å)                                        55 Gb/s (2500 Å)
              
             55 Gb/s (3000 Å)                                         55 Gb/s (3500 Å)
Fig. 5   Output signal simulation for different bitrates and different Wc
Fig. 6   MUX-Driver module measurement (40 Gb/s 2,2 Vpp)


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Technological and geometrical optimisation of InP HBT driver circuit

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AMS Acta - Alm@DL - Università di Bologna

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AMS Acta