Interaction Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study

In this work, we report a theoretical study based on quantum transport simulations that show the impact of the surface roughness on the performance of ultimately scaled gate-all-around silicon nanowire transistors (SNWT) with precisely positioned dopants designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green's Function (NEGF) formalism is used. The individual dopants and the profile of the channel surface roughness act as localized scatters and, hence, the impact on the electron transport is directly correlated to the combined effect of position of the single dopants and surface roughness shape. As a result, a large variation in the IOFF and ION and modest variation of the subthreshold slope are observed in the ID-VG characteristics when comparing devices without surface roughness. The variations of the current-voltage characteristics are analyzed with reference to the behaviour of the transmission coefficients, electron potential and electron concentration along the length of the device. Our calculations provide guidance for a future development of the next generation components with sub-10 nm dimensions for the semiconductor industry

Impact of randomly distributed dopants on Ω-gate junctionless silicon nanowire transistors

This paper presents experimental and simulation analysis of an Ω-shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/μm for 1.0 V and 2.52 mA/μm for the 1.8-V gate overdrive with an OFF-current set at 100 nA/μm. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current-voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ID-VGs characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ID-VGs characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs

Interactions Between Precisely Placed Dopants and Interface Roughness in Silicon Nanowire Transistors: Full 3-D NEGF Simulation Study

Abstract-In this work, we report a theoretical study based on quantum transport simulations that show the impact of the surface roughness on the performance of ultimately scaled gateall-around silicon nanowire transistors (SNWT) with precisely positioned dopants designed for digital circuit applications. Due to strong inhomogeneity of the self-consistent electrostatic potential, a full 3-D real-space Non Equilibrium Green's Function (NEGF) formalism is used. The individual dopants and the profile of the channel surface roughness act as localized scatters and, hence, the impact on the electron transport is directly correlated to the combined effect of position of the single dopants and surface roughness shape. As a result, a large variation in the I OFF and I O

Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels

Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories

Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

The experimental results from 8 nm diameter silicon nanowire junctionless field effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/m for 1.0 V and 2.52 mA/m for 1.8 V gate overdrive with an off-current set at 100 nA/m. On- to off-current ratios above 108 with a subthreshold slope of 66 mV/dec are demonstrated at 25 oC. Simulations using drift-diffusion which include densitygradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps

Capacitance fluctuations in bulk MOSFETs due to random discrete dopants

Accuracy of timing in circuits and systems using nanoscale transistors is crucial and is dependent, to first order, on the capacitances of the load transistors. It is accepted that variation in parameters will be intrinsic to such devices due to, among other factors, the discrete nature of the doping. It is likely that one such parameter exhibiting variation will be capacitance. Here we investigate, using 3-dimensional simulation, the fluctuation in gate and drain capacitance in a 30 nm MOSFET due to random discrete doping

Hierarchical Statistical 3D ' Atomistic' Simulation of Decanano MOSFETs: Drift-Diffusion, Hydrodynamic and Quantum Mechanical Approaches

When MOSFETs are scaled to deep submicron dimensions the discreteness and randomness of the dopant charges in the channel region introduces significant fluctuations in the device characteristics. This effect, predicted 20 year ago, has been confirmed experimentally and in simulation studies. The impact of the fluctuations on the functionality, yield, and reliability of the corresponding systems shifts the paradigm of the numerical device simulation. It becomes insufficient to simulate only one device representing one macroscopical design in a continuous charge approximation. An ensemble of macroscopically identical but microscopically different devices has to be characterized by simulation of statistically significant samples. The aims of the numerical simulations shift from predicting the characteristics of a single device with continuous doping towards estimating the mean values and the standard deviations of basic design parameters such as threshold voltage, subthreshold slope, transconductance, drive current, etc. for the whole ensemble of 'atomistically' different devices in the system. It has to be pointed out that even the mean values obtained from 'atomistic' simulations are not identical to the values obtained from continuous doping simulations. In this paper we present a hierarchical approach to the 'atomistic' simulation of aggressively scaled decanano MOSFETs. A full scale 3D drift-diffusion'atomostic' simulation approach is first described and used for verification of the more economical, but also more restricted, options. To reduce the processor time and memory requirements at high drain voltage we have developed a self-consistent option based on a thin slab solution of the current continuity equation only in the channel region. This is coupled to the Poisson's equation solution in the whole simulation domain in the Gummel iteration cycles. The accuracy of this approach is investigated in comparison with the full self-consistent solution. At low drain voltage only single solution of the nonlinear Poisson equation is sufficient to extract the current with satisfactory accuracy. A pilot version of a hydrodynamic 'atomistic' simulator has been developed in order to study the effect of the nonequilibrium, non local transport in decanano MOSFETs on the random dopant induced current fluctuations. For the first time we have also applied the density gradient approach in 3D to investigate the effect of the quantum confinement on the threshold voltage fluctuations. The developed 'atomistic' simulation techniques have been applied to study various fluctuation resistant MOSFET architectures including epitaxial and delta doped devices

Perturbative vs non-perturbative impurity scattering in a narrow Si nanowire GAA transistor: A NEGF study

In this paper we study the effect of impurity scattering on the performance of a Si gate-all-around nanowire transistors. The non-equilibrium Green function formalism is used in order to describe the carrier transport. Impurity scattering is introduced using two different formalisms, one that considers the impurity potential as a small perturbation by introducing self energies and the other in which the impurity potential is described exactly by included the impurity potential through the Poisson equation. The non-perturbative method does not use a fitting parameter but the perturbative one uses a phenomenological constant that can be calibrated to match the result of the non-perturbative method. We confirm Ohms-law-type behaviour by using the perturbative approach for larger channel length