Transparent Memory Encryption and Authentication

Security features of modern (SoC) FPAGs permit to protect the confidentiality of hard- and software IP when the devices are powered off as well as to validate the authenticity of IP when being loaded at startup. However, these approaches are insufficient since attackers with physical access can also perform attacks during runtime, demanding for additional security measures. In particular, RAM used by modern (SoC) FPGAs is under threat since RAM stores software IP as well as all kinds of other sensitive information during runtime. To solve this issue, we present an open-source framework for building transparent RAM encryption and authentication pipelines, suitable for both FPGAs and ASICs. The framework supports various ciphers and modes of operation as shown by our comprehensive evaluation on a Xilinx Zynq-7020 SoC. For encryption, the ciphers Prince and AES are used in the ECB, CBC and XTS mode. Additionally, the authenticated encryption cipher Ascon is used both standalone and within a TEC tree. Our results show that the data processing of our encryption pipeline is highly efficient with up to 94% utilization of the read bandwidth that is provided by the FPGA interface. Moreover, the use of a cryptographically strong primitive like Ascon yields highly practical results with 54% bandwidth utilization

Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers

Reduction of the power consumption in portable wireless receivers is important for cellular systems, including UMTS and IMT2000. This paper explores the architectural design-space and methodologies for reducing the dynamic power dissipation in the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink RAKE receiver. At the algorithm level, we investigate the tradeoffs of reduced precision and arithmetic complexity on the receiver performance. We then present and analyse two architectures for implementing the reference and reduced complexity receivers, with respect to dynamic power dissipation. The combined effect of reduced precision and complexity reduction leads to a 37.44% power savings.Nokia CorporationTexas Instruments Inc.National Science Foundatio

A parallel implementation of sequential minimal optimization on FPGA

This paper proposes a parallel FPGA implementation of the training phase of a Support Vector Machine (SVM). The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO implementation is also highly parallel and uses some acceleration techniques, such as the error cache. Moreover, the Hardware Friendly Kernel (HFK) is used in order to reduce the kernel’s area, enabling an increase in the number of kernels per area. After the parallel implementation in hardware, the SVM is validated by bit-accurate simulation. Finally, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGAs area usage is performed

The mechanical characteristic of rock salt under uniaxial compression with low temperature effect

he mechanical characteristic of rock salt under uniaxial compression after effected by temperature was studied. The test temperature were 35, 50, 70°C. The results shown that: the Stress-strain curve of rock salt effected with low temperature under uniaxial compression process are similar, Which illustrated that the mechanical behavior of the salt rock specimen with room temperature can reflect the characteristics rock salt of rock salt underground. It is means that rock salt under the condition of short-term temperature drying effect, its mechanical characteristics was unchanged. Generally rock salt effected by temperature in the process of uniaxial compression, its acoustic emission ringing shown the similar property. The uniaxial mechanical properties was similar, when the rock salt specimens effected with temperature from 35 to 70°C

A flexible low-cost, high-precision, single interface electrical impedance tomography system for breast cancer detection using FPGA

Typically, in multi-frequency Electrical Impedance Tomography (EIT) systems, a current is applied and the voltages developed across the subject are detected. However, due to the complexity of designing stable current sources, there has been mention in the literature of applying a voltage to the subject whilst measuring the consequent current flow. This paper presents a comparative study between the two techniques in a novel design suitable for the detection of breast cancers. The suggested instrument borrows the best features of both the injection of current and the application of voltage, circumventing their limitations. Furthermore, the system has a common patient-electrode interface for both methodologies, whilst the control of the system and the necessary signal processing is carried out in a field programmable gate array (FPGA). Through this novel system, wide-bandwidth, low-noise, as well as high-speed (frame rate) can be achieved

Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

<p>Abstract</p> <p>Background</p> <p>This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA) devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM) is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences).</p> <p>Results</p> <p>This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM) resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs.</p> <p>Conclusion</p> <p>Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.</p

Diabetes and lipid screening among patients in primary care: A cohort study

<p>Abstract</p> <p>Background</p> <p>Obesity is associated with increased cardiovascular diseases and diabetes mellitus. Guidelines call for intensified glucose and lipid screening among overweight and obese patients. Data on compliance with these guidelines are scarce. The purpose of this study was to assess rates of diabetes and lipid screening in primary care according to demographic variables and weight status.</p> <p>Methods</p> <p>Over a 3-year follow-up period, we assessed screening rates for blood glucose, triglycerides, and HDL- and LDL-cholesterol among 5025 patients in primary care. From proportional hazards models we estimated screening rates among low, moderate, high, and very-high risk patients and compared them with recommendations of the American Diabetes Association (ADA), National Cholesterol Education Program (ATP III) and U.S. Preventive Services Task Force (USPSTF).</p> <p>Results</p> <p>Mean (SD) age was 47.4 (15.6); 69% were female, 21% were non-white, and 30% of males and 25% of females were obese (BMI ≥ 30 kg/m²). For both diabetes and lipid screening, the adjusted hazard was 260–330% higher among ≥65 than <35 year-olds, 50–90% higher in persons with BMI ≥ 35 than <25 kg/m², 10–30% lower for females than males, and not lower among racial/ethnic minorities. Screening rates were at least 80% among very-high risk persons, which we defined as 55–64 years old, BMI ≥ 35 kg/m², non-white, with baseline hypertension. In contrast, high-risk persons who were younger (35–44 years old) and less obese (BMI 30–<35 kg/m²) were screened less often (43% for LDL-cholesterol among females to 83% for diabetes among males) even though ADA, ATP III and USPSTF recommend diabetes and lipid screening among them.</p> <p>Conclusion</p> <p>Patients with higher BMI or age were more likely to be screened for cardiometabolic risk factors. Women were screened at lower rates than men. Even in a highly structured medical group practice, some obese patients were under-screened for diabetes and dyslipidemia.</p

Geppetto: a reusable modular open platform for exploring neuroscience data and models

Geppetto is an open-source platform that provides generic middleware infrastructure for building both online and desktop tools for visualizing neuroscience models and data and managing simulations. Geppetto underpins a number of neuroscience applications, including Open Source Brain (OSB), Virtual Fly Brain (VFB), NEURON-UI and NetPyNE-UI. OSB is used by researchers to create and visualize computational neuroscience models described in NeuroML and simulate them through the browser. VFB is the reference hub for Drosophila melanogaster neural anatomy and imaging data including neuropil, segmented neurons, microscopy stacks and gene expression pattern data. Geppetto is also being used to build a new user interface for NEURON, a widely used neuronal simulation environment, and for NetPyNE, a Python package for network modelling using NEURON. Geppetto defines domain agnostic abstractions used by all these applications to represent their models and data and offers a set of modules and components to integrate, visualize and control simulations in a highly accessible way. The platform comprises a backend which can connect to external data sources, model repositories and simulators together with a highly customizable frontend.This article is part of a discussion meeting issue 'Connectome to behaviour: modelling C. elegans at cellular resolution'