CMOS design of cellular APAPs and FPAPAPs: an overview

CNN-based analog visual microprocessors have similarities with the so-called Single Instruction Multiple Data systems, although they work directly on analog signal representations obtained through embedded optical sensors and hence do not need a frontend sensory plane or analog-to-digital converters. The architecture of these visual microprocessors is illustrated in the paper through two prototype chips, namely: ACE4K and ACE16K. In both cases, as in other related chips the architecture includes a core array of interconnected elementary processing units, surrounded by a global circuitry.Office of Naval Research N00014-00-10429Comisión Interministerial de Ciencia y Tecnología TIC-1999-082

Accurate and simple modeling of amplifier dc gain nonlinearity in switched-capacitor circuits

This paper presents an accurate and simple model for dc gain nonlinearity of operational amplifiers used in the switched-capacitor circuits such as the sigma-delta modulators. The proposed model can simply be used in the time-domain system level simulation of sigma-delta modulators to evaluate the effect of amplifier's dc gain nonlinearity on the overall linearity of the modulator as well as in the other switched- capacitor circuits as explored in the paper.Comisión Interministerial de Ciencia y Tecnología TIC2003-0235

Switched-Current Chaotic Neurons

The Letter presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks. They have been fabricated in a double-metal, single-poly 1.6µm CMOS technology. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realise piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3V) with a clock frequency of 500 kHz

Learning in neuro/fuzzy analog chips

This paper focus on the design of adaptive mixed-signal fuzzy chips. These chips have parallel architecture and feature electrically-controlable surface maps. The design methodology is based on the use of composite transistors - modular and well suited for design automation. This methodology is supported by dedicated, hardware-compatible learning algorithms that combine weight-perturbation and outstar

Modular Design of Adaptive Analog CMOS Fuzzy Controller Chips

Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level -- prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5μm single-poly technology

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

CMOS current-mode chaotic neurons

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJT's. They have been fabricated in a double-metal, single-poly 1.6 /spl mu/m CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in the current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploration of the exponential-law operation of CMOS-BJT's. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

A 64-channel inductively-powered neural recording sensor array

This paper reports a 64-channel inductively powered neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor and transferred to the outside by means of the same inductive link used for powering the system. Simulation results show that the power consumption of the complete system is 377μW.Ministerio de Ciencia e Innovación TEC2009-0844