Cyclic redundancy check-based detection algorithms for automatic identification system signals received by satellite.

This paper addresses the problem of demodulating signals transmitted in the automatic identification system. The main characteristics of such signals consist of two points: (i) they are modulated using a trellis-coded modulation, more precisely a Gaussian minimum shift keying modulation; and (ii) they are submitted to a bit stuffing procedure, which makes more difficult the detection of the transmitted information bits. This paper presents several demodulation algorithms developed in different contexts: mono-user and multi-user transmissions, and known/unknown phase shift. The proposed receiver uses the cyclic redundancy check (CRC) present in the automatic identification system signals for error correction and not for error detection only. By using this CRC, a particular Viterbi algorithm, on the basis of a so-called extended trellis, is developed. This trellis is defined by extended states composed of a trellis code state and a CRC state. Moreover, specific conditional transitions are defined to take into account the possible presence of stuffing bits. The algorithms proposed in the multi-user scenario present a small increase of computation complexity with respect to the mono-user algorithms. Some performance results are presented for several scenarios in the context of the automatic identification system and compared with those of existing techniques developed in similar scenarios

Special issue on satellite communication systems and networking

[No abstract available

Advanced receiver design for satellite-based automatic identification system signal detection

This paper describes an innovative receiver architecture for the satellite-based automatic identification system. The receiver performance has been fully validated in the presence of the typical satellite channel characteristics. In particular, it is shown that the devised receiver provides an excellent performance against the noise, as well as a large resilience against message collisions, Doppler shift, and delay spread

FLEXIBLE CHANNEL DECODER

A configurable Turbo-LDPC decoder comprising: - A set of P>1 Soft-Input-Soft-Output decoding units (DP0 - DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I1 i) and second (I2 i) input ports and first (O1 i) and second (O2 i) output ports for intermediate data; First and second memories (M1, M2) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory