Field Plate Design for Low Leakage Current in Lateral GaN Power Schottky Diodes: Role of the Pinch-Off Voltage

In this letter, we demonstrate a general model to reduce the reverse leakage current (I-R) in high-voltage AlGaN/GaN Schottky diodes (SBDs) by engineering the pinchoff voltage (V-p) of their field plates (FPs). The maximum voltage drop at the Schottky junction (V-SCH) in the OFF state can be significantly decreased by reducing vertical bar V-p vertical bar, which leads to a drastically diminished I-R. We used a tri-gate architecture as means to control V-p and, thus, I-R, as it offers great flexibility to engineer V-p compared with conventional schemes. vertical bar V-p vertical bar of SBDs with tri-gate FPs was reduced by decreasing the width of the nanowires, which led to a very small I-R, below 10 nA/mm under reverse biases up to 500 V, and an increase of over 800 V in soft breakdown voltage (V-BR) at 1 mu A/mm. These results reveal the importance of V-p in reducing I-R for SBDs, and unveil the potential of tri-gate structures as FPs for power devices

Calibration of Drive Non-Linearity for Arbitrary-Angle Single-Qubit Gates Using Error Amplification

The ability to execute high-fidelity operations is crucial to scaling up quantum devices to large numbers of qubits. However, signal distortions originating from non-linear components in the control lines can limit the performance of single-qubit gates. In this work, we use a measurement based on error amplification to characterize and correct the small single-qubit rotation errors originating from the non-linear scaling of the qubit drive rate with the amplitude of the programmed pulse. With our hardware, and for a 15-ns pulse, the rotation angles deviate by up to several degrees from a linear model. Using purity benchmarking, we find that control errors reach $2\times 10^{-4}$, which accounts for half of the total gate error. Using cross-entropy benchmarking, we demonstrate arbitrary-angle single-qubit gates with coherence-limited errors of $2\times 10^{-4}$ and leakage below $6\times 10^{-5}$. While the exact magnitude of these errors is specific to our setup, the presented method is applicable to any source of non-linearity. Our work shows that the non-linearity of qubit drive line components imposes a limit on the fidelity of single-qubit gates, independent of improvements in coherence times, circuit design, or leakage mitigation when not corrected for

Fast Flux-Activated Leakage Reduction for Superconducting Quantum Circuits

Quantum computers will require quantum error correction to reach the low error rates necessary for solving problems that surpass the capabilities of conventional computers. One of the dominant errors limiting the performance of quantum error correction codes across multiple technology platforms is leakage out of the computational subspace arising from the multi-level structure of qubit implementations. Here, we present a resource-efficient universal leakage reduction unit for superconducting qubits using parametric flux modulation. This operation removes leakage down to our measurement accuracy of $7\cdot 10^{-4}$ in approximately $50\, \mathrm{ns}$ with a low error of $2.5(1)\cdot 10^{-3}$ on the computational subspace, thereby reaching durations and fidelities comparable to those of single-qubit gates. We demonstrate that using the leakage reduction unit in repeated weight-two stabilizer measurements reduces the total number of detected errors in a scalable fashion to close to what can be achieved using leakage-rejection methods which do not scale. Our approach does neither require additional control electronics nor on-chip components and is applicable to both auxiliary and data qubits. These benefits make our method particularly attractive for mitigating leakage in large-scale quantum error correction circuits, a crucial requirement for the practical implementation of fault-tolerant quantum computation

Germanium Quantum-Well Josephson Field-Effect Transistors and Interferometers

International audienc

Realizing quantum convolutional neural networks on a superconducting quantum processor to recognize quantum phases

Quantum computing crucially relies on the ability to efficiently characterize the quantum states output by quantum hardware. Conventional methods which probe these states through direct measurements and classically computed correlations become computationally expensive when increasing the system size. Quantum neural networks tailored to recognize specific features of quantum states by combining unitary operations, measurements and feedforward promise to require fewer measurements and to tolerate errors. Here, we realize a quantum convolutional neural network (QCNN) on a 7-qubit superconducting quantum processor to identify symmetry-protected topological (SPT) phases of a spin model characterized by a non-zero string order parameter. We benchmark the performance of the QCNN based on approximate ground states of a family of cluster-Ising Hamiltonians which we prepare using a hardware-efficient, low-depth state preparation circuit. We find that, despite being composed of finite-fidelity gates itself, the QCNN recognizes the topological phase with higher fidelity than direct measurements of the string order parameter for the prepared states.ISSN:2041-172