The challenges Chinese academic staff face in the University of Nottingham in terms of culture

The internationalization in higher education is very popular around the word. The United Kingdom has many great universities that are famous and highly ranked around the world, and attract students from different countries. The internationalization in the higher education institutions in the UK is very common, and almost each university has international students and international academic staff. The different educational background and cultural background rich the cultural diversity, however, also bring challenges to international academic staff. Therefore, this paper aims to research the challenges international academic staff face in terms of culture and discuss the influence of that. The paper will choose Chinese academic staff in the Nottingham university as research subjective, since Chinese academic staff are now the top group of international academic staff in the UK, and the state system and educational context are quite different between China and UK. The paper will use semi-structured interview as research method to find the challenges and influence of culture on them

Small-Area SAR ADCs With a Compact Unit-Length DAC Layout

This brief presents four small-area SAR ADCs with a resolution from 8 to 11 bits. Two area-saving techniques are utilized. First, the DAC layout is implemented with custom designed unit-length capacitors, which are optimized for each resolution to minimize the chip area. Second, dynamic logic is applied to the 8-bit design to further reduce the number of transistors and save area. Fabricated in 65 nm CMOS, the 8/9/10/11-bit SAR ADCs only occupy 20times 21,,mu text{m} , 20times 36,,mu text{m} , 36times 36,,mu text{m} and 36times 36,,mu text{m} , respectively. At 10 MHz sampling rate, their measured ENOB is 7.5, 8.3, 9.1 and 9.8 bits with an SFDR of 65.4 dB, 67.4 dB, 78.0 dB and 76.5 dB, respectively. Compared to prior-art, these designs achieve the smallest areas for the achieved ENOBs.</p

A 10-bit 4 MS/s SAR ADC with Fully-Dynamic Duty-Cycled Input Driver

This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.</p

InfeRE: Step-by-Step Regex Generation via Chain of Inference

Automatically generating regular expressions (abbrev. regexes) from natural language description (NL2RE) has been an emerging research area. Prior studies treat regex as a linear sequence of tokens and generate the final expressions autoregressively in a single pass. They did not take into account the step-by-step internal text-matching processes behind the final results. This significantly hinders the efficacy and interpretability of regex generation by neural language models. In this paper, we propose a new paradigm called InfeRE, which decomposes the generation of regexes into chains of step-by-step inference. To enhance the robustness, we introduce a self-consistency decoding mechanism that ensembles multiple outputs sampled from different models. We evaluate InfeRE on two publicly available datasets, NL-RX-Turk and KB13, and compare the results with state-of-the-art approaches and the popular tree-based generation approach TRANX. Experimental results show that InfeRE substantially outperforms previous baselines, yielding 16.3% and 14.7% improvement in DFA@5 accuracy on two datasets, respectively. Particularly, InfeRE outperforms the popular tree-based generation approach by 18.1% and 11.3% on both datasets, respectively, in terms of DFA@5 accuracy.Comment: This paper has been accepted by ASE'2

A 0.0033 mm²3.5 fJ/conversion-step SAR ADC with 2× Input Range Boosting

This paper proposes an input range boosting technique for successive-approximation-register (SAR) analog-to-digital converters (ADC). By performing a pre-comparison and switching the DAC accordingly, the input range of a SAR ADC can be doubled with limited power and area overhead. This effectively improves the power efficiency by relaxing the noise requirement and improves the area efficiency by using less DAC capacitors. A prototype ADC is fabricated in 65 nm CMOS and occupies an area of 0.0033 mm2. It consumes 34.06μW at 10 MHz sampling rate from a 1 V supply. The measured SNDR is 62 dB for a 5 MHz bandwidth, resulting in a Walden figure of merit (FoMW) of 3.28 fJ/conversion step.</p

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled G_m-C Integrator

This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming 13.5μ W, leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.</p

A SAR ADC with Reconfigurable Delay and Redundancy to Relax the Reference Driver

This work presents a reconfigurable delay and redundancy technique, which relaxes the reference driver requirements for a charge-redistribution SAR ADC. By selectively adding delay to the most critical SAR cycle, the overall speed of the ADC is only slightly degraded, while the output impedance of the driver or the amount of decoupling capacitance can be reduced substantially. In a simulated 10-bit 10 MS/s SAR ADC prototype, the proposed technique reduces the decoupling capacitance by 16× while maintaining 59.2 dB SNDR and 71.2 dB SFDR at a power consumption of 32 mu mathrm{W}. The estimated area is 0.002 mm2 including decoupling capacitors.</p