ADDING PERFECT FORWARD SECRECY TO KERBEROS

Kerberos system is a powerful and widely implemented authentication system. Despite this fact it has several problems such as the vulnerability to dictionary attacks which is solved with the use of public key cryptography. Also an important security feature that is not found in Kerberos is perfect forward secrecy. In this work the lack of this feature is investigated in Kerberos in its original version. Also a public key based modification to Kerberos is presented and it is shown that it lacks the prefect forward secrecy too. Then some extensions are proposed to achieve this feature. The extensions are based on public key concepts (Diffie-Hellman) with the condition of keeping the password based authentication; this requires little modifications to the original Kerberos. Four extensions are proposed; two of them modify the (Client-Authentication Server) exchange achieving conditional perfect forward secrecy, while the remaining two modify the Client-Server exchange achieving perfect forward secrecy but with increased overhead and delay

Comparative Reliability Analysis between Horizontal-Vertical-Diagonal Code and Code with Crosstalk Avoidance and Error Correction for NoC Interconnects

Ensuring reliable data transmission in Network on Chip (NoC) is one of the most challenging tasks, especially in noisy environments. As crosstalk, interference, and radiation were increased with manufacturers' increasing tendency to reduce the area, increase the frequencies, and reduce the voltages.  So many Error Control Codes (ECC) were proposed with different error detection and correction capacities and various degrees of complexity. Code with Crosstalk Avoidance and Error Correction (CCAEC) for network-on-chip interconnects uses simple parity check bits as the main technique to get high error correction capacity. Per this work, this coding scheme corrects up to 12 random errors, representing a high correction capacity compared with many other code schemes. This candidate has high correction capability but with a high codeword size. In this work, the CCAEC code is compared to another well-known code scheme called Horizontal-Vertical-Diagonal (HVD) error detecting and correcting code through reliability analysis by deriving a new accurate mathematical model for the probability of residual error Pres for both code schemes and confirming it by simulation results for both schemes. The results showed that the HVD code could correct all single, double, and triple errors and failed to correct only 3.3 % of states of quadric errors. In comparison, the CCAEC code can correct a single error and fails in 1.5%, 7.2%, and 16.4% cases of double, triple, and quadric errors, respectively. As a result, the HVD has better reliability than CCAEC and has lower overhead; making it a promising coding scheme to handle the reliability issues for NoC

Reliability analysis of multibit error correcting coding and comparison to hamming product code for on-chip interconnect

Error control schemes became a necessity in network-on-chip (NoC) to improve reliability as the on-chip interconnect errors increase with the continuous shrinking of geometry. Accordingly, many researchers are trying to present multi-bit error correction coding schemes that perform a high error correction capability with the simplest design possible to minimize area and power consumption. A recent work, Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB), showed a huge reduction in area and power consumption compared to a well-known scheme, namely, Hamming product code (HPC) with Type-II HARQ. Moreover, the authors showed that the proposed scheme can correct 11 random errors which is considered a high number of errors to be corrected by any scheme used in NoC. The high correction capability with moderate number of check bits along with the reduction in power and area requires further investigation in the accuracy of the reliability model. In this paper, reliability analysis is performed by modeling the residual error probability Presidual which represents the probability of decoder error or failure. New model to estimate Presidual of MECCRLB is derived, validated against simulation, and compared to HPC to assess the capability of MECCRLB. The results show that HPC outperforms MECCRLB from reliability perspective. The former corrects all single and double errors, and fails in 5.18% cases of the triple errors, whereas the latter is found to correct all single errors but fails in 32.5% of double errors and 38.97% of triple errors

Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects

In this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links

Adaptive multibit crosstalk-aware error control coding scheme for on-chip communication

The presence of different noise sources and continuous increase in crosstalk in the deep submicrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achieves up to 25.3% power savings at 3-mm wire length as compared to the original nonadaptive scheme at the cost of only 3.4% power overhead in high protection mode

Area efficient test circuit for library standard cell qualification

High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction

Investigating the impact of on-chip interconnection noise on dynamic thermal management efficiency

Dynamic Thermal Management (DTM) emerged as a solution to address the reliability challenges with thermal hotspots and unbalanced temperatures. DTM efficiency is highly affected by the accuracy of the temperature information presented to the DTM manager. This work aims to investigate the effect of inaccuracy caused by the deep sub-micron (DSM) noise during the transmission of temperature information to the manager on DTM efficiency. A simulation framework has been developed and results show up to 62% DTM performance degradation under DSM noise. The finding highlights the importance of further research in providing reliable on-chip data transmission in DTM application

Improved undetected error probability model for JTEC and JTEC-SQED coding schemes

The undetected error probability is an important measure to assess the communication reliability provided by any error coding scheme. Two error coding schemes namely, Joint crosstalk avoidance and Triple Error Correction (JTEC) and JTEC with Simultaneous Quadruple Error Detection (JTEC-SQED), provide both crosstalk reduction and multi-bit error correction/detection features. The available undetected error probability model yields an upper bound value which does not give accurate estimation on the reliability provided. This paper presents an improved mathematical model to estimate the undetected error probability of these two joint coding schemes. According to the decoding algorithm the errors are classified into patterns and their decoding result is checked for failures. The probabilities of the failing patterns are used to build the new models. The improved models have less than 1% error with respect to the simulation results and reflect in up to 60% higher mean time to failure as compared to available models

A fast feature extraction algorithm for image and video processing

Medical images and videos are utilized to discover, diagnose and treat diseases. Managing, storing, and retrieving stored images effectively are considered important topics. The rapid growth of multimedia data, including medical images and videos, has caused a swift rise in data transmission volume and repository size. Multimedia data contains useful information; however, it consumes an enormous storage space. Therefore, high processing time for that sheer volume of data will be required. Image and video applications demand for reduction in computational cost (processing time) when extracting features. This paper introduces a novel method to compute transform coefficients (features) from images or video frames. These features are used to represent the local visual content of images and video frames. We compared the proposed method with the traditional approach of feature extraction using a standard image technique. Furthermore, the proposed method is employed for shot boundary detection (SBD) applications to detect transitions in video frames. The standard TRECVID 2005, 2006, and 2007 video datasets are used to evaluate the performance of the SBD applications. The achieved results show that the proposed algorithm significantly reduces the computational cost in comparison to the traditional method

Crosstalk-aware error control coding techniques for reliable and energy efficient network on chip

With the continuous downscaling in semiconductor technology more blocks are being integrated in a single chip. Network on Chip (NoC) represents the main solution for the increased on chip communication complexity. One of the major challenges in NoC is the communication reliability due to the small feature sizes, high operating frequency and low operating voltage of the chips. Achieving reliable operation under the influence of deep-submicron noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this work, new joint coding schemes are proposed to provide high level of protection from errors and simultaneously reduce the crosstalk induced bus delay. The proposed coding schemes are based on wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This Duplicated Two-Dimensional Parities (DTDP) coding provides high Hamming distance allowing high error protection capability. In addition, the duplication technique addresses crosstalk delay effects allowing higher bus frequency operation. The high error protection capability enables the reduction of wires operating voltage while maintaining the target reliability level, leading to power/energy savings. For a given Hamming distance, providing only error detection without correction provides the highest possible protection. Accordingly, the first proposed coding scheme is based on automatic repeat request (ARQ) policy providing up to seven errors detection, thus named DTDP-7ED. On the other hand, the second proposed coding scheme is based on hybrid ARQ (HARQ) policy. Single error correction capability is added to reduce the retransmission probability which comes on the cost of reduced error detection capability, resulting in single error correction and six error detection (DTDP-SEC6ED). The two proposed schemes allow for higher reduction in voltage swing as compared to other joint coding schemes which reflects into higher power savings. Since DTDP-7ED has the highest error detection which results into the lowest voltage swing, it achieved the highest power savings. On the other hand, DTDP-SEC6ED achieved lower energy consumption and higher performance. We also propose a coding scheme that jointly provides crosstalk delay reduction and adaptable error protection according to noise severity. This was motivated by the inefficient energy consumption of traditional designs that constantly work assuming worst case noise scenario. The scheme works in one of three modes by duplicating the data bits, the data bits and one-dimensional parities, or the data bits and two dimensional parities at low, intermediate, and high noise conditions respectively. The maximum protection mode achieves 51.1% energy savings over Duplicate Add Parity (DAP) coding scheme. This energy savings is increased to 59.5% and 63.0% at intermediate and low protection modes respectively. This comes with a comparable area and maximum frequency compared to other similar coding schemes