Automated Layout-integrated Sizing of a 2.45 GHz Differential-Drive Rectifier in 28 nm FDSOI CMOS

Rectifiers are considered key analog blocks to power the energy-autonomous wireless applications envisioned by the Internet-of-Things. However, their design routine is still a time consuming process as the layout step requires human intervention at each iteration of the optimization phase. The layout parasitic effects (e.g. well-proximity effects) introduced by this step can have a non-negligible impact on circuit performances, especially when targeting high-efficiency operation at UHF in the ultra-low power range, where parasitics have a higher impact. In this paper, we propose an automatic sizing and layout integrated methodology, based on commercial digital place and route tools, to optimize the cross-coupled/differential-drive rectifier architecture, including post-layout verification, in an advanced 28nm FDSOI CMOS process. A genetic and a gradient optimization methods are compared to increase the time-efficiency of the methodology. A 3-stage rectifier is optimized, providing 1.17 μW under 1 μA load at 2.45 GHz with 68% efficiency