A multimodal cell census and atlas of the mammalian primary motor cortex

ABSTRACT We report the generation of a multimodal cell census and atlas of the mammalian primary motor cortex (MOp or M1) as the initial product of the BRAIN Initiative Cell Census Network (BICCN). This was achieved by coordinated large-scale analyses of single-cell transcriptomes, chromatin accessibility, DNA methylomes, spatially resolved single-cell transcriptomes, morphological and electrophysiological properties, and cellular resolution input-output mapping, integrated through cross-modal computational analysis. Together, our results advance the collective knowledge and understanding of brain cell type organization: First, our study reveals a unified molecular genetic landscape of cortical cell types that congruently integrates their transcriptome, open chromatin and DNA methylation maps. Second, cross-species analysis achieves a unified taxonomy of transcriptomic types and their hierarchical organization that are conserved from mouse to marmoset and human. Third, cross-modal analysis provides compelling evidence for the epigenomic, transcriptomic, and gene regulatory basis of neuronal phenotypes such as their physiological and anatomical properties, demonstrating the biological validity and genomic underpinning of neuron types and subtypes. Fourth, in situ single-cell transcriptomics provides a spatially-resolved cell type atlas of the motor cortex. Fifth, integrated transcriptomic, epigenomic and anatomical analyses reveal the correspondence between neural circuits and transcriptomic cell types. We further present an extensive genetic toolset for targeting and fate mapping glutamatergic projection neuron types toward linking their developmental trajectory to their circuit function. Together, our results establish a unified and mechanistic framework of neuronal cell type organization that integrates multi-layered molecular genetic and spatial information with multi-faceted phenotypic properties

Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)

In the pursuit of alternatives to optical lithography, block copolymer directed self-assembly (DSA) has emerged as a low-cost, high-throughput option. DSA uses small topographical templates to contain the block copolymer and create small clusters of holes useful for patterning vias [1]. However, issues of defectivity have hampered DSA' s viability for large-scale patterning. Recent studies have shown polymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures [2]. The inherent density variations in via layouts, though, make regions of overfilled templates nearly inevitable, as templates in less dense regions will contain more polymer. For this reason, we develop a method to integrate sub-DSA resolution assist features (SDRAFs) into DSA template layouts. The SDRAFs divert excess polymer from the overfilled main templates but are themselves too small to form transferrable DSA patterns [2]. Thus, we can populate low-density regions with SDRAFs to make a layout more uniformly dense. To do this, we use SDRAFs with a set of lithography-based design rules dictating the minimum pitch and resist thickness between features (95 nm and 45 nm for 193i, respectively). The SDRAF CD is also chosen to be as large as possible without forming a transferrable DSA pattern, setting it at 40 nm for an L0 = 40 nm polymer and a PS wetting flow. With these rules, we set a flow for the assignment of each SDRAF according to the calculated density of templates in each block. We demonstrate the process on a 2.5 x 2.5 um section from V23 (the via layer connecting metals 2 and 3) of a routed N7 Cortex-M0 processor scaled to a 24 nm via layout grid. We first overlay the template layout with a grid of SDRAFs spaced at 96 nm, allowing the SDRAFs to align with the via grid. We then remove the SDRAFs that violate the minimum resist or pitch rules and assess the density result. This is done by dividing the layout into blocks and calculating the percentage of area occupied by the main and assist templates in the blocks, using prior experimental data for template area [3]. The size of the blocks is set to the length over which the polymer reflows during the thermal anneal [4], assumed here to be about 500 nm. Finally, the SDRAF grid is shifted vertically and horizontally in increments of the via grid (24 nm) to achieve different density results, as each shift causes different SDRAFs to be in violation. We can then choose the shift that minimizes the density variation across the blocks as the final layout. In our test case, we found that the density range of the blocks changed from 2.8-8.6% to 10.9-12.9% post-SDRAF assignment. Here, the polymer film thickness can be adjusted to accommodate the higher overall density and the narrowed density range shows promise to reduce template overfill. Future work will incorporate methods of improving the layout's PV band to create an SDRAF design strategy that is more DSA- and lithography-friendly. [1] H. Yi et al., Adv. Mater 24, 23 (2012). [2] H. Yi et al., Proc. SPIE 9423, 1F (2015). [3] J. Doise et al., J. Vac. Sci. Technol. B 33, 6 (2015). [4] H. Yi et al., Proc. SPIE 9323, 2A (2015).status: publishe

Self-assembly for electronics

Self-assembly, a process in which molecules, polymers, and particles are driven by local interactions to organize into patterns and functional structures, is being exploited in advancing silicon electronics and in emerging, unconventional electronics. Silicon electronics has relied on lithographic patterning of polymer resists at progressively smaller lengths to scale down device dimensions. Yet, this has become increasingly difficult and costly. Assembly of block copolymers and colloidal nanoparticles allows resolution enhancement and the definition of essential shapes to pattern circuits and memory devices. As we look to a future in which electronics are integrated at large numbers and in new forms for the Internet of Things and wearable and implantable technologies, we also explore a broader material set. Semiconductor nanoparticles and biomolecules are prized for their size-, shape-, and composition-dependent properties and for their solution-based assembly and integration into devices that are enabling unconventional manufacturing and new device functions.

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

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Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Major advancements in the directed self-assembly (DSA) of block copolymers have shown the technique’s strong potential for via/contact layer patterning in advanced technology nodes. Molecular scale pattern precision along with low cost processing promotes DSA technology as a great candidate for complementing conventional photolithography. Our studies show that decomposition of via layers with 193-nm immersion lithography in realistic circuits below the 7-nm node would require a prohibitive number of multiple patterning steps. The grouping of vias through templated DSA can resolve local conflicts in high density areas, limiting the number of required masks, and thus cutting a great deal of the associated costs. A design method for DSA via patterning in sub-7-nm nodes is discussed. We present options to expand the list of usable DSA templates and we formulate cost functions and algorithms for the optimal DSA-aware via layout decomposition. The proposed method works a posteriori, after place-and-route, allowing for fast practical implementation. We tested this method on a fully routed 32-bit processor designed for sub-7 nm technology nodes. Our results demonstrate a reduction of up to four lithography masks when compared to conventional non-DSA-aware decomposition.status: publishe

Design Strategy for Integrating DSA Via Patterning in sub-7 nm Interconnects

In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7 nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of lithography masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where via hole patterns are readily produced through templated confinement of cylindrical phase BCP materials. Our in-house studies show that decomposition of via layers in realistic circuits below the 7 nm node would require at least many multi-patterning steps (or colors), using 193 nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vial through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced. To implement this approach, a DSA-aware mask decomposition is required. In this paper, a design method for DSA via patterning in sub-7 nm nodes is discussed. We present options to expand the list of DSA-compatible via patterns (DSA letters). Additionally, we define cost formulas and we develop a tool for the optimal DSA-aware layout decomposition. This method is tested on a fully routed processor, demonstrating a reduction of up to four lithography masks, when compared to conventional non-DSA-aware decomposition

Unveiling the Effect of Superlattice Interfaces and Intermixing on Phase Change Memory Performance

Superlattice (SL) phase change materials have shown promise to reduce the switching current and resistance drift of phase change memory (PCM). However, the effects of internal SL interfaces and intermixing on PCM performance remain unexplored, although these are essential to understand and ensure reliable memory operation. Here, using nanometer-thin layers of Ge2Sb2Te5 and Sb2Te3 in SL-PCM, we uncover that both switching current density (J(reset)) and resistance drift coefficient (v) decrease as the SL period thickness is reduced (i.e., higher interface density); however, interface intermixing within the SL increases both. The signatures of distinct versus intermixed interfaces also show up in transmission electron microscopy, X-ray diffraction, and thermal conductivity measurements of our SL films. Combining the lessons learned, we simultaneously achieve low J(reset) & AP; 3-4 MA/ cm(2) and ultralow v & AP; 0.002 in mushroom-cell SL-PCM with similar to 110 nm bottom contact diameter, thus advancing SL-PCM for and neuromorphic applications