Establishing and evaluating FRAX® probability thresholds in Taiwan

Background/purpose: The Taiwanese FRAX® calculator was launched in 2010. However, cost-effectiveness thresholds for the prescription of antiosteoporosis medications were not established. This study aims to establish and evaluate FRAX®-based probability thresholds in Taiwan. Methods: Using previous data from Taiwan and literature, we determined cost-effectiveness thresholds for prevention of osteoporotic fractures by alendronate with a Markov model, as well as using two other translational approaches. Sensitivity analysis was applied using different alendronate prices. A clinical sample was used to test these Taiwan-specific thresholds by determining the percentages of high-risk patients who would be qualified for current National Health Insurance reimbursement. Results: With the Markov model, the intervention threshold for hip fracture was 7% for women and 6% for men; for major osteoporotic fracture, it was 15% for women and 12.5% for men. Both translational approach models were cost effective only for certain age groups. However, if branded alendronate was reimbursed at 60% of the current price, they became cost effective in almost all age groups. This clinical screening study showed that the National Health Insurance Administration model identified the highest proportion (44%) of patients qualified for National Health Insurance reimbursements, followed by the Markov model (30%), and the United States model (22%). Conclusion: Three FRAX®-based models of alendronate use were established in Taiwan to help optimize treatment strategies. The government is encouraged to incorporate FRAX®-based approaches into the reimbursement policy for antiosteoporosis medicines

Zasady higjeny szkolnej : podręcznik przeznaczony do użytku nauczycieli, kierowników szkół i lekarzy szkolnych

[2], VII, [1], 297 s. ; 22 cm

On the design, control, and use of a reconfigurable heterogeneous multi-core system-on-a-chip

With the continued progress in VLSI technologies, we can integrate numerous cores in a single billion-transistor chip to build a multi-core system-on-a-chip (SoC). This also brings great challenges to traditional parallel programming as to how we can increase the performance of applications with increased number of cores. In this paper, we meet the challenges using a novel approach. Specifically, we propose a reconfigurable heterogeneous multi-core system. Under our proposed system, in addition to conventional processor cores, we introduce dynamically reconfigurable accelerator cores to boost the performance of applications. We have built a prototype of the system using FPGAs. Experimental evaluation demonstrates significant system efficiency of the proposed heterogeneous multi-core system in terms of computation and power consumption. ©2008 IEEE.link_to_subscribed_fulltex

Computation and energy efficient image processing in wireless sensor networks based on reconfigurable computing

In a wireless sensor network, each node is power-constrained and may need to acquire some raw data of large size (e.g., image data), on which some computationintensive tasks (e.g., edge detection) will be done. On the other hand, in wireless communication, significant power will be consumed on transferring a sequence of data of large size. Thus, it is of high interest to carry out the sensor nodes' computation-intensive tasks efficiently while reducing the data size for wireless transfer. In this paper, we propose a new design methodology for batch processing of image data in a wireless sensor network, by employing reconfigurable computing using FPGAs. © 2006 IEEE.link_to_subscribed_fulltex

Practical design of a computation and energy efficient hardware task scheduler in embedded reconfigurable computing systems

By utilizing massively parallel circuit design in FPGAs, the overall system efficiency, in terms of computation efficiency and energy efficiency, can be greatly enhanced by offloading some computation-intensive tasks which are originally executed in the instruction set processor to the. FPGA fabric. In essence, a hardware task scheduler is needed. However, most of the work in the literature considers scheduling algorithms which are. unable or difficult to be implemented using the design flows in current development platform. Moreover, little of the work takes energy consumption into consideration. In this paper, we present the design of a hardware task scheduler which takes energy consumption into consideration, and can be readily implemented using current design flows. © 2006 IEEE.link_to_subscribed_fulltex

On the design of a self-reconfigurable SoPC based cryptographic engine

This paper presents a SoPC (System-on-a-Programmable-Chip) embedded system featuring self-reconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported in this paper show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA.link_to_subscribed_fulltex