Activation of cAMP signaling transiently inhibits apoptosis in vascular smooth muscle cells in a site upstream of caspase-3

Intracellular signaling pathways that are involved in protection of vascular smooth muscle cells (VSMC) from apoptosis remain poorly understood. This study examines the effect of activators of cAMP/cGMP signaling on apoptosis in non-transfected VSMC and in VSMC transfected with c-myc (VSMC-MYC) or with its functional analogue, E1A-adenoviral protein (VSMC-E1A). Serum-deprived VSMC-E1A exhibited the highest apoptosis measured as the content of chromatin and low molecular weight DNA fragments, phosphatidylserine content in the outer surface of plasma membrane and caspase-3 activity (ten-, five-, four- and tenfold increase after 6 h of serum withdrawal, respectively). In VSMC-E1A, the addition of an activator of adenylate cyclase, forskolin, abolished chromatin cleavage, DNA laddering, caspase-3 activation and the appearance of morphologically-defined apoptotic cells triggered by 6 h of serum deprivation. In non-transfected VSMC and in VSMC-MYC, 6 h serum deprivation led to approximately six- and threefold activation of chromatin cleavage, respectively, that was also blocked by forskolin. In VSMC-E1A, inhibition of apoptosis was observed with other activators of cAMP signaling (cholera toxin, isoproterenol, adenosine, 8-Br-cAMP), whereas 6 h incubation with modulators of cGMP signaling (8-Br-cGMP, nitroprusside, atrial natriuretic peptide, L-NAME) did not affect the development of apoptotic machinery. The antiapoptotic effect of forskolin was abolished in 24 h of serum deprivation that was accompanied by normalization of intracellular cAMP content and protein kinase A (PKA) activity. Protection of VSMC-E1A from apoptosis by forskolin was blunted by PKA inhibitors (H-89 and KT5720), whereas transfection of cells with PKA catalytic subunit attenuated apoptosis triggered by serum withdrawal. The protection of VSMC-E1A by forskolin from apoptosis was insensitive to modulators of cytoskeleton assembly (cytochalasin B, colchicine). Neither acute (30 min) nor chronic (24 h) exposure of VSMC to forskolin modified basal and serum-induced phosphorylation of the MAP kinase ERK1/2. Thus, our results show that activation of cAMP signaling delays the development of apoptosis in serum-deprived VSMC at a site upstream of caspase-3 via activation of PKA and independently of cAMP-induced reorganization of the cytoskeleton network and the ERK1/2-terminated MAPK signaling cascade

3D Reconstruction of the Neurovascular Unit Reveals Differential Loss of Cholinergic Innervation in the Cortex and Hippocampus of the Adult Mouse Brain

Increasing evidence supports a role for cerebrovasculature dysfunction in the etiology of Alzheimer’s disease (AD). Blood vessels in the brain are composed of a collection of cells and acellular material that comprise the neurovascular unit (NVU). The NVU in the hippocampus and cortex receives innervation from cholinergic neurons that originate in the basal forebrain. Death of these neurons and their nerve fibers is an early feature of AD. However, the effect of the loss of cholinergic innervation on the NVU is not well characterized. The purpose of this study was to evaluate the effect of the loss of cholinergic innervation of components of the NVU at capillaries, arteries and veins in the hippocampus and cortex. Adult male C57BL/6 mice received an intracerebroventricular injection of the immunotoxin p75NTR mu-saporin to induce the loss of cholinergic neurons. Quadruple labeling immunohistochemistry and 3D reconstruction were carried out to characterize specific points of contact between cholinergic fibers and collagen IV, smooth muscle cells and astrocyte endfeet. Innate differences were observed between vessels of the hippocampus and cortex of control mice, including a greater amount of cholinergic contact with perivascular astrocytes in hippocampal capillaries and a thicker basement membrane in hippocampal veins. Saporin treatment induced a loss of cholinergic innervation at the arterial basement membrane and smooth muscle cells of both the hippocampus and the cortex. In the cortex, there was an additional loss of innervation at the astrocytic endfeet. The current results suggest that cortical arteries are more strongly affected by cholinergic denervation than arteries in the hippocampus. This regional variation may have implications for the etiology of the vascular pathology that develops in AD

Integrated switched-capacitor-based cold-start circuit for DC-DC energy harvesters with wide input/output voltage range and low inductance in 40-nm CMOS

This paper outlines an integrated switched-capacitor (SC)-based cold-start circuit for dc-dc energy harvesters that uniquely combines a low cold-start voltage, wide input/output voltage and low inductance value in the boost stage. The proposed design specifically targets size-constrained, self-powered Internet-of-Things applications. The proposed design is an SC circuit built from low-threshold-voltage devices operating in the sub-threshold region and provides the drive voltage for high-threshold-voltage devices of the boost dc-dc converter. The SC circuit is an NMOS-based Dickson charge pump driven synchronously with a series of cross-coupled voltage doublers and voltage multiplying gate drivers. The SC circuit, which is integrated together with a boost converter as the dc-dc energy harvester, has been implemented in a 40-nm CMOS process for future system-on-chip integration. The measured results show that with a 4.7 μH boost converter inductance, the design can start up from typical input voltages as low as 190 mV while offering up to 2.4 V input and 5 V output voltage compatibility

Improved dynamics in DC-DC converters for IoT applications with repetitive load profiles using self-calibrated preemptive current control

This paper presents a novel approach to improve the dynamic response of inductive dc-dc converters in applications having repetitive load profiles. In many Internet-of-Things (IoT) applications, such as wireless sensor networks (WSN), the load current profile has a periodic nature, and is therefore predictable by the power management circuits. This unique nature is exploited by the proposed Preemptive Concurrent Controller (PCC) to achieve a dynamic response superior to the theoretical limits of time-optimal control. The preemptive controller ramps up the inductor current prior to the occurrence of a load step and reduces the required output capacitance. The non-inverting buck-boost converter is used in this work and operates with a freewheeling mode that avoids output voltage overshoot during the preemptive inductor current ramp. Two hysteric control loops operate concurrently to define the freewheeling interval. A simple digital calibration scheme is demonstrated to extract timing and amplitude features from a load current profile in order to optimize the timing of the preemptive current reference in the next cycle. Freewheeling is thus minimized to increase system efficiency. The PCC and associated load profile learning algorithm is experimentally verified and uses 10× less capacitance compared to the time-optimal control benchmark

A cell-level power management IC in BCD-SOI for partial power processing in Concentrating-PV systems

This work presents a power management IC used to mitigate the effects of mismatch in Concentrating-Photovoltaic (CPV) systems. The IC contains a bi-directional dc-dc converter, an auxiliary boost converter to generate the internal 10 V power supply, as well as protection and monitoring circuits. The main power converter, with a maximum current rating of 1.5 A, is designed to equalize the voltage between neighbouring CPV cells by using the ¿-converter approach. Due to partial power processing, the converter's power rating and efficiency requirements are relaxed, leading to a more cost-effective solution with a high switching frequency of 3.6 MHz. An on-chip, mixed-signal controller regulates the main converter using a digital voltage loop and an analog hysteretic current-mode loop. The IC has several advanced features to reduce the light-load power consumption, including burst-mode operation in both the auxiliary and main-stage converters, as well as an input supply switching scheme for the internal linear voltage regulators

A dual-mode driver IC with monolithic negative drive-voltage capability and digital current-mode controller for depletion-mode GaN HEMT

This work presents a driver and controller integrated circuit (IC) for depletion-mode gallium nitride (GaN) high-electron-mobility transistors (HEMTs). The dual-mode driver can be configured for cascode-drive (CD) or HEMT-drive (HD) mode. In the CD mode, a cascode low-voltage DMOS is driven to achieve high-speed normally OFF operation. An active clamping circuit is proposed for the DMOS breakdown protection. In the HD mode, an HEMT gate driver with negative drive-voltage capability and programmable slope control is presented. A digital peak current-mode controller is also integrated with the dual-mode driver. The IC was implemented in a 140-nm automotive bipolar-CMOS-DMOS silicon-on-insulator process. The driver/controller IC is copackaged with an optimized 600-V GaN HEMT fabricated in a GaN-on-Si process. The solution was verified to operate at up to 1 MHz in a 35-W boost converter prototype and achieves a programmable switching-node dv/dt of up to 20 V/ns. To the best of the author's knowledge, this is the first monolithic integration of a cascode MOSFET, device driver, and digital current-mode controller that is designed specifically for high-voltage GaN devices

A GaN HEMT driver IC with programmable slew rate and monolithic negative gate-drive supply and digital current-mode control

This work presents an intelligent driver IC for 400 V GaN-based Power Factor Correction (PFC) applications. The targeted power level of the converter is 100 W, with a switching frequency above 500 kHz. The IC was implemented in a 140 nm automotive BCD SOI process, while the GaN HEMT and Schottky diode were optimized in a Si-fab compatible GaN-on-Si process. A low-Ron DMOS is integrated in the driver IC to achieve high-speed cascode switching operation. The chip also features a novel dual-mode drive scheme with monolithic negative drive voltage capability and programmable slew rate, as well as a digital peak current-mode controller. Advanced digital PFC control schemes can therefore be implemented, while EMC performance and efficiency can be optimized through active slope control

A cell-level power management IC in BCD-SOI for partial power processing in Concentrating-PV systems

This work presents a power management IC used to mitigate the effects of mismatch in Concentrating-Photovoltaic (CPV) systems. The IC contains a bi-directional dc-dc converter, an auxiliary boost converter to generate the internal 10 V power supply, as well as protection and monitoring circuits. The main power converter, with a maximum current rating of 1.5 A, is designed to equalize the voltage between neighbouring CPV cells by using the ¿-converter approach. Due to partial power processing, the converter's power rating and efficiency requirements are relaxed, leading to a more cost-effective solution with a high switching frequency of 3.6 MHz. An on-chip, mixed-signal controller regulates the main converter using a digital voltage loop and an analog hysteretic current-mode loop. The IC has several advanced features to reduce the light-load power consumption, including burst-mode operation in both the auxiliary and main-stage converters, as well as an input supply switching scheme for the internal linear voltage regulators