Design of a wide-bandwidth on-chip antenna for uncooled passive THz imaging

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High-resolution dielectric characterization of minerals: a step towards understanding the basic interactions between microwaves and rocks

Microwave energy was demonstrated to be potentially beneficial for reducing the cost of several steps of the mining process. Significant literature was developed about this topic but few studies are focused on understanding the interaction between microwaves and minerals at a fundamental level in order to elucidate the underlying physical processes that control the observed phenomena. This is ascribed to the complexity of such phenomena, related to chemical and physical transformations, where electrical, thermal and mechanical forces play concurrent roles. In this work a new characterization method for the dielectric properties of mineral samples at microwave frequencies is presented. The method is based upon the scanning microwave microscopy technique that enables measurement of the dielectric constant, loss factor and conductivity with extremely high spatial resolution and accuracy. As opposed to conventional dielectric techniques, the scanning microwave microscope can then access and measure the dielectric properties of micrometric-sized mineral inclusions within a complex structure of natural rock. In this work two micrometric hematite inclusions were characterized at a microwave frequency of 3 GHz. Scanning electron microscopy/energy-dispersive x-ray spectroscopy and confocal micro-Raman spectroscopy were used to determine the structural details and chemical and elemental composition of mineral sample on similar scale

Timing, Trigger and Control Systems for LHC Detectors

\\ \\At the LHC, precise bunch-crossing clock and machine orbit signals must be broadcast over distances of several km from the Prevessin Control Room to the four experiment areas and other destinations. At the LHC experiments themselves, quite extensive distribution systems are also required for the transmission of timing, trigger and control (TTC) signals to large numbers of front-end electronics controllers from a single location in the vicinity of the central trigger processor. The systems must control the detector synchronization and deliver the necessary fast signals and messages that are phased with the LHC clock, orbit or bunch structure. These include the bunch-crossing clock, level-1 trigger decisions, bunch and event numbers, as well as test signals and broadcast commands. A common solution to this TTC system requirement is expected to result in important economies of scale and permit a rationalization of the development, operational and support efforts required. LHC Common Project RD12 is developing a multi-function optoelectronic TTC system which can meet the requirements of central signal broadcasting and local distribution at the different subdetectors of the experiments. A laser transmitter, modulator, encoder, VMEbus interface and machine interface are being developed as well as a subminiature radiation-hard optical fibre connector, active device mount and photodetector/preamplifier. A radiation-hard timing receiver ASIC is being designed which will generate the full range of decoded signals for electronics controllers from a single in put and a PMC receiver module is being developed to facilitate initial applications. The system incorporates programmable coarse and fine deskew facilities to compensate for different particle flight times and detector, electronics, propagation and test generator delays. It can also transmit asynchronous slow controls and data such as individually-addressed channel enables and calibration parameters to several thousand destinations

RD12 project collaboration TTCrx Reference Manual A Timing, Trigger and Control Receiver ASIC for LHC Detectors

Version 3.1

G-link and gigabit ethernet compliant serializer for LHC data transmission

Gbit/s data transmission links will be used in several LHC detectors in trigger and data acquisition systems. In these experiments, the transmitters will be subject to high radiation doses over the lifetime of the experiments. In this work, a radiation tolerant transmitter ASIC is described. The JC supports two standard protocols, the G-Link and the Gbit-Ethernet, and sustains transmission of data at both 800 Mbit/s and 1.6 Gbit/s. The ASIC was implemented in a mainstream 0.25mum CMOS technology employing radiation tolerant layout practices. A 1.2 Gbit/s prototype with reduced functionality was tested. The ASIC behavior under total dose irradiation as well as its susceptibility to single event upsets was studied and the results are reported here. 12 Refs

A Radiation Tolerant Gigabit Serializer for LHC Data Transmission

In the future LHC experiments, some data acquisition and trigger links will be based on Gbit/s optical fiber networks. In this paper, a configurable radiation tolerant Gbit/s serializer (GOL) is presented that addresses the high-energy physics experiments requirements. The device can operate in four different modes that are a combination of two transmission protocols and two data rates (0.8 Gbit/s and 1.6 Gbit/s). The ASIC may be used as the transmitter in optical links that, otherwise, use only commercial components. The data encoding schemes supported are the CIMT (G-Link) and the 8B/10B (Gbit-Ethernet & Fiber Channel). To guarantee robustness against total dose irradiation effects over the lifetime of the experiments, the IC was fabricated in a standard 0.25 µm CMOS technology employing radiation tolerant layout practices. The device was exposed to different irradiation sources to test its sensitivity to total dose effects and to single effects upsets. For this tests, a comparison is established with a commercial serializer. I

A 90GS/s 8b 667mW 64x Interleaved SAR ADC in 32nm Digital SOI CMOS

A 90GS/s 8b low-power ADC is presented achieving 33.0-36.0dB SNDR and a FoM of 203fJ/conversion-step. High conversion speed of up to 100GS/s and high input bandwidth of 22GHz is achieved by using a 1:64 interleaver with integrated sampling. Single NMOS transistors followed by 1:4 demux stages are used to sample the signal. Skew and gain adjustment is implemented on-chip. The ADC consumes 667mW at 90GS/s and 845mW at 100GS/s and can be operated from a single supply voltage. It is implemented in 32nm SOI CMOS and occupies 0.45mm2