Bus Interconnect Structure for a System-on-a-Chip Multiprocessor System

This report describes two possible implementations for a bus interconnect structure which would be used in a multiprocessor System-On-a-Chip. The bus architecture is called the GGBA (General Global Bus Architecture.) The research findings presented in this report show that from two possible implementations for a system bus for this bus architecture, one of those would be the most advantageous based on factors such as bus latency, crosstalk, and bus area

Kinematic analysis of epicyclic bevel gear trains with matroid method

The paper presents a novel technique for the kinematic analysis of bevel gear trains using the incidence matrices of an edge-oriented graph of the mechanism. The kinematic equations are then obtained in matrix form using a cycle basis from a cycle matroid. These equations can be systematically generated, and allow for an efficient computation of the angular velocities of the gears and planet carriers of the mechanism without employing time derivative operations. As illustrated in the paper, the method is applicable to bevel gear trains of any number of gears or degrees of freedom

A GENERAL METHOD OF KINEMATIC ANALYSIS OF PARALLEL AXES EPICYCLIC GEAR TRAINS BASED ON GRAPH-CYCLE MATROID THEORY

A novel method for kinematic analysis of parallel-axes epicyclic gear trains (EGT) is presented, called the incidence and transfer method (IT), which uses the incidence matrices associated to the edge-oriented graph attached to the mechanism and the transfer joints (teeth contact joints). Relative to such joints, a set of independent equations can be generated for calculating the angular positions, velocities, and accelerations. Complete kinematic equations are obtained in matrix form using a base of circuits from a cycle matroid. The analysis uses the relationships between the number of mobile links, number of joints, and number of circuits in the base of circuits, together with the Latin matrix (whose entries are function of the absolute values of the partial gear ratios of the transmission). Singularities, like groups of gears that rotate as a whole, can be identified by calculating the rank of the Latin matrix. Relationships between the output and input angular velocities and accelerations are then determined in a matrix-based approach, without using any derivative operations. The proposed method has general applicability and can be employed for systems with any number of gears and degrees of freedom, as illustrated by the numerical examples presented

Kinematic Singularities of a 3-DoF Planar Geared Robot Manipulator

International audienceBy incorporating gearing into a planar 3R mechanism, one obtains a family of mechanisms in which the gear ratios play a central kinematic role. Special choices of these parameters result in interesting simplifications of the kinematic mapping. An explicit expression for the mapping can be derived using the 'matroid method' of Talpasanu et al [7]. We use this relatively simple mechanism to illustrate singularity analysis for geared mechanisms

Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC

As feature size is scaled down to the submicron level, interconnect delay in the design of a high-speed System-on-a-Chip (SoC) becomes a major concern. This concern is especially acute for on-chip buses. In this paper we describe a methodology to generate a custom bus architecture using accurate estimations of interconnect delay. To improve bus delay accuracy, the bus Verilog register-transfer level (RTL) specification was altered based on interconnect delay estimations. Interconnect delay information is provided from an estimated chip layout. The delay estimates for the on-chip buses are used early in the design phase with a corresponding impact on system correctness and performance. As an example of interconnect delay aware bus generation, we compare three different General Global Bus Architecture (GGBA) configurations, showing that certain system blocks (the memory controllers) need to be modified based on interconnect delay estimation. The three different GGBA configurations are evaluated through the simulation of an orthogonal frequency division multiplexing (OFDM) wireless transmitter application. The impact of accurate interconnect delay estimation is shown through a 35.3 % reduction in execution time between a worstcase bus delay configuration (GGBA III) and an accurate interconnect delay aware GGBA configuration (GGBA II). 1