Analysis of Phase Noise and Jitter in Ring Oscillators

Voltage controlled oscillators (VCOs) have gain paramount importance in frequency modulation (FM) and pulse modulation (PM) circuits, phase locked loops (PLLs), function generators, frequency synthesizers etc. which are vital for communication circuits. CMOS based ring oscillators have tuning range, tuning gain and phase noise as the important characteristics. The most difficult task is that variation of phase due to stochastic perturbations. Phase noise has been the designer’s primary concerned. The effect of oscillator’s noise is one of the most insightful issues in the designing of modern RF telecommunication systems. A low phase noise with minimum power dissipation is rapidly preferred criteria for the design of voltage controlled ring oscillators (VCROs). A very simple and precise analysis of different phase noise models of ring VCOs and their causes is analyzed in this paper. For each case, the flicker noise and the white noise component of phase noise and jitter are considered which limits the signal. The important elements that determine the phase noise in VCOs are the transistor's flicker noise ( noise), the output power level, and the quality factor (Q). A synchronized relationship among the effective noise components in the oscillatory circuits leads to good agreement for new design insights and also improves the performance. Keywords: Ring Oscillators, Voltage Controlled Oscillator, Voltage Controlled Ring Oscillator, Phase noise, jitter

Design of Low Voltage Improved performance Current Mirror

This paper proposes a low voltage current mirror circuit with low input impedance and high output impedance. These improvements are obtained by adding an amplifier which provides biasing voltage to the transistors. Its operation and results are compared with conventional and cascode current mirror circuits. The circuits are designed using Tanner EDA Tool in 90nm CMOS technology with 0.8V supply voltage. Simulation results shows that the minimum output voltage is reduced to 0.1 V, also input resistance is reduced to 0.179k? and consumes only 46µW power. Keywords: Current mirror, Input resistance Output resistance, Input compliance voltage, Output compliance voltage

Design of Low Offset and High Speed CMOS Comparator for Analog to Digital Converter

In today’s world everything is digitized but nature is analog, so it is necessary to have such a device which converts analog signal into digital and for this analog to digital converter is required. Now a day’s ADC’s require lesser power, better slew rate, high speed and less offset. Performance limiting component for ADC’s are amplifiers and comparators in which comparator is the most important.This paper presents the design of low offset low power dissipation and high speed  comparator. The proposed comparator consists of a preamplifier stage, decision stage and self biased output buffer stage. The proposed design uses a low power current mirror circuitry for providing a highly biased current. The circuit is designed using 90nm CMOS process for a supply voltage of 1V and reference voltage of 0.5V and power consumption is approximately 300?W. Keywords: CMOS Comparator, Current Mirror, Pre Amplifier, Output Buffe

250 MHz Multiphase Delay Locked Loop for Low Power Applications

Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz

Design of Operational Transconductance Amplifier using Double Gate MOSFET

Operational Ttransconductance Amplifier is very popular in analog electronics industry due to its vast applications. Analog integrated circuits have been widely used for high frequency applications. OTA has number of applications like filters, analog multipliers and analog dividers. Double gate MOSFETs (DG-MOSFETs) are strong contenders for nano scale region due its better control over short channel effects. DG-MOSFET can be used in analog circuit applications as a four-terminal device. Back gate bias can be used for better tunability. The double gate based circuits provide additional gains in terms of area, power and speed. This paper presents double gate based OTA which has high gain over a wide bandwidth. The simulation results shows gain of 9.32 dB and bandwidth is 7GHz.The simulations are done using Tanner EDA Software Tool at 90nm technology. Keywords: DG MOSFETs, OTA, Analog tunable circuits, Gain, Wide bandwidth, CMOS Process, Double gates, Self cascode techniqu

Design of Second Order Low Pass and High Pass Filter using Double Gate MOSFET based OTA

OTA-C filters are one of the most widely used as continuous time filters. It is because they are fast active integrators, provides low-power operation and tuning of the filter characteristics at higher frequencies. At high frequencies, the OP AMP based active filters has limited performance. We cannot change the values of resistors and inductors but OTA-C filter provides ability to change their values by changing the transconductance of OTA. Second order low and high pass filter structures have widespread applications. The double gate MOSFETs show better performance in the nanometer range of operation. Because it has better control over short channel effects (SCE’s) and other scaling related problems like gate leakage, sub-threshold conduction. Double gate MOSFET is four terminal device and back gate can be used for biasing which can tune the characteristics of circuit. This will provide additional advantage of low power and reduced area. This paper presents second order low pass and high pass filter based on double gate OTA for VHF and UHF frequency applications. The proposed filter consists of two OTAs and two capacitors. This filter shows low sensitivity to passive components, low component count and ease in design.  The simulation results shows pass band frequency of 14MHz and power consumption of 153.4 µwatt. The simulations are done using Tanner EDA version 13.0 at 90nm technology. Keywords: DG MOSFETs; OTA-C; Analog tunable circuits; Gain; Bandwidth; Double gate; Self cascode technique; Low pass filter; High pass filter

Single Electron Transistor Based Current Mirror: Modelling and Performance Characterization

Current mirror is basic building block of amplifier, oscillator and comparator circuit. An ideal current mirror is independent of input power and temperature. The output current is constant mirrored image of input current. In order to avoid wrong equilibrium it must have high output impedance. This can be achieved by using super cascode formation. The single electron coulomb blockade structure provides low voltage operation and scaling of transistor to 10 nm. The Single Electron Transistor (SET) based CM is modeled and analyzed by simulation and the results shows improved performance of CM

Design of Ultra Low Power Integrated PLL using Ring VCO

The design of an ultra low power Phase Locked Loop (PLL) is presented in this paper. The proposed PLL consists of a phase detector, a charge pump, low pass filter, and a ring oscillator based voltage controlled oscillator (VCO). The performance of Voltage Controlled Oscillator is of great importance for PLL. The circuit is designed using 0.13µm CMOS technology with the supply voltage of 1V and has a power consumption of 254µW. Keywords: Charge Pump, CMOS Technology, Low Pass Filter, Phase Detector, Phase Locked Loop, Voltage Controlled Oscillator

Aceclofenac induced morbilliform eruptions: a case report

Maculopapular or morbilliform eruptions may be the most common of all cutaneous drug reactions. Antimicrobials, NSAIDS, barbiturates, anticonvulsants, oral hypoglycemics etc. have been commonly implicated in these adverse reactions (ADR). Here, authors are presenting a case of a 38-year-old female with morbilliform eruptions due to aceclofenac for the treatment of joint pain. The patient was treated with antihistaminics, steroids, antimicrobials and local application of GV paint. She was discharged after eleven days with good recovery

Design of Ring Oscillator based VCO with Improved Performance

Voltage Controlled Oscillator plays significant role in communication system design. The design of Voltage Controlled Oscillator (VCO) with low power consumption and high frequency range is presented in this paper. The VCO is based on a single ended CMOS inverter ring oscillator. Accurate frequency of oscillation in Ring Oscillator is an important design issue. A Voltage Controlled Ring Oscillator with wide tuning range from 917.43MHz to 4189.53MHz can be achieved using bulk driven technique by varying the threshold voltage of the MOS circuits. The circuit is designed using 0.13µm CMOS process for a supply voltage of 1V. Simulation results show better accuracy compared to existing current staved ring VCO using different number of inverter stages. Keywords: Bulk driven technique, CMOS Process, Ring Oscillator, Voltage Controlled Ring Oscillator, Inverter