W and Z Production in pp Collisions at 7TeV with ATLAS

Measurements of W and Z cross-sections in pp collisions at ECM = 7 TeV at the Large Hadron Collider are reported from the ATLAS experiment. From an observation of 118 leptonic W candidates, the inclusive W cross-section times leptonic branching fraction is measured as [9.3 \pm 0.9(stat) \pm 0.6(syst) \pm 1.0(lumi)] nb. The result for the Z boson is [0.83 \pm 0.07(stat) \pm 0.06(syst) \pm 0.09(lumi)] nb. These results agree with theoretical expectations from NNLO QCD.Comment: 3 pages, 6 figure

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover

Moving formal methods into practice. Verifying the FTPP Scoreboard: Results, phase 1

This report documents the Phase 1 results of an effort aimed at formally verifying a key hardware component, called Scoreboard, of a Fault-Tolerant Parallel Processor (FTPP) being built at Charles Stark Draper Laboratory (CSDL). The Scoreboard is part of the FTPP virtual bus that guarantees reliable communication between processors in the presence of Byzantine faults in the system. The Scoreboard implements a piece of control logic that approves and validates a message before it can be transmitted. The goal of Phase 1 was to lay the foundation of the Scoreboard verification. A formal specification of the functional requirements and a high-level hardware design for the Scoreboard were developed. The hardware design was based on a preliminary Scoreboard design developed at CSDL. A main correctness theorem, from which the functional requirements can be established as corollaries, was proved for the Scoreboard design. The goal of Phase 2 is to verify the final detailed design of Scoreboard. This task is being conducted as part of a NASA-sponsored effort to explore integration of formal methods in the development cycle of current fault-tolerant architectures being built in the aerospace industry

On Feature Binding in Space and Time

When presented with a yellow Volkswagen and a red Ferrari, how does the brain ?gure out which color goes with which car? The binding problem refers to how the visual system pre-consciously combines visual features of objects in the physical world to create coherent mental equivalents in our consciousness. I discuss why feature binding is a problem for our brains despite its seemingly e?ortless resolution in every-day life. Drawing from experimental cognitive psychology, I demonstrate how it manifests in space and time

The formal verification used for the AAMP5 and AAMP-FV

The main goal of the project was two-fold: First, to investigate the feasibility of formally specifying and verifying a complex commercial microprocessor that was not expressly designed for formal verification. Second, to explore effective ways to transfer the technology to an industrial setting. The choice of the AAMP5 satisfied the first goal since the AAMP5 was not designed for formal verification, but to provide a more than threefold performance improvement while remaining object-code-compatible with the earlier AAMP2, which is used in numerous avionics applications, including the Boeing 737, 747, 757, and 767. To satisfy the technology transfer objective, we had to develop a suitable verification methodology and a formal infrastructure to make the technology usable by practicing engineers. This infrastructure includes techniques for decomposing the microcompressor verification problem into a st of verification conditions that the engineers can formulate and strategies to automate the proof of the verification conditions. The development of the infrastructure was one of the key accomplishments of the project. Most of the infrastructure and methodology are general enough to be reused for other microprocessors, certainly in the verification of another member of the AAMP family. This methodology was used to formally specify the entire microarchitecture and more than half of the instruction set and to verify a core set of eleven AAMP5 instructions representative of several instruction classes. However, the methodology and the formal machinery developed are adequate to cover most of the remaining AAMP5 instructions. Although PVS was the vehicle of the experiment, the methodology is applicable to other sufficiently powerful theorem provers

The cost of space independence in P300-BCI spellers.

Background: Though non-invasive EEG-based Brain Computer Interfaces (BCI) have been researched extensively over the last two decades, most designs require control of spatial attention and/or gaze on the part of the user. Methods: In healthy adults, we compared the offline performance of a space-independent P300-based BCI for spelling words using Rapid Serial Visual Presentation (RSVP), to the well-known space-dependent Matrix P300 speller. Results: EEG classifiability with the RSVP speller was as good as with the Matrix speller. While the Matrix speller’s performance was significantly reliant on early, gaze-dependent Visual Evoked Potentials (VEPs), the RSVP speller depended only on the space-independent P300b. However, there was a cost to true spatial independence: the RSVP speller was less efficient in terms of spelling speed. Conclusions: The advantage of space independence in the RSVP speller was concomitant with a marked reduction in spelling efficiency. Nevertheless, with key improvements to the RSVP design, truly space-independent BCIs could approach efficiencies on par with the Matrix speller. With sufficiently high letter spelling rates fused with predictive language modelling, they would be viable for potential applications with patients unable to direct overt visual gaze or covert attentional focus

Neurocognitive and Neuroplastic Mechanisms of Novel Clinical Signs in CRPS.

Complex regional pain syndrome (CRPS) is a chronic, debilitating pain condition that usually arises after trauma to a limb, but its precise etiology remains elusive. Novel clinical signs based on body perceptual disturbances have been reported, but their pathophysiological mechanisms remain poorly understood. Investigators have used functional neuroimaging techniques (including MEG, EEG, fMRI, and PET) to study changes mainly within the somatosensory and motor cortices. Here, we provide a focused review of the neuroimaging research findings that have generated insights into the potential neurocognitive and neuroplastic mechanisms underlying perceptual disturbances in CRPS. Neuroimaging findings, particularly with regard to somatosensory processing, have been promising but limited by a number of technique-specific factors (such as the complexity of neuroimaging investigations, poor spatial resolution of EEG/MEG, and use of modeling procedures that do not draw causal inferences) and more general factors including small samples sizes and poorly characterized patients. These factors have led to an underappreciation of the potential heterogeneity of pathophysiology that may underlie variable clinical presentation in CRPS. Also, until now, neurological deficits have been predominantly investigated separately from perceptual and cognitive disturbances. Here, we highlight the need to identify neurocognitive phenotypes of patients with CRPS that are underpinned by causal explanations for perceptual disturbances. We suggest that a combination of larger cohorts, patient phenotyping, the use of both high temporal, and spatial resolution neuroimaging methods, and the identification of simplified biomarkers is likely to be the most fruitful approach to identifying neurocognitive phenotypes in CRPS. Based on our review, we explain how such phenotypes could be characterized in terms of hierarchical models of perception and corresponding disturbances in recurrent processing involving the somatosensory, salience and executive brain networks. We also draw attention to complementary neurological factors that may explain some CRPS symptoms, including the possibility of central neuroinflammation and neuronal atrophy, and how these phenomena may overlap but be partially separable from neurocognitive deficits.This is the final version of the article. It first appeared from Frontiers via http://dx.doi.org/10.3389/fnhum.2016.0001

Verifying an interactive consistency circuit: A case study in the reuse of a verification technology

The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation of a scheme for attaining interactive consistency (byzantine agreement) among four microprocessors is presented in view graph form. The microprocessors used in the design are an updated version of a formally verified 32-bit, instruction-pipelined, RISC processor, MiniCayuga. The 4-processor system, which is designed under the assumption that the clocks of all the processors are synchronized, provides software control over the interactive consistency operation. Interactive consistency computation is supported as an explicit instruction on each of the microprocessors. An identical user program executing on each of the processors decides when and on what data interactive consistency must be performed. This exercise also served as a case study to investigate the effectiveness of reusing the technology which was developed during the MiniCayuga effort for verifying synchronous hardware designs. MiniCayuga was verified using the verification system Clio which was also developed at ORA. To assist in reusing this technology, a computer-aided specification and verification tool was developed. This tool specializes Clio to synchronous hardware designs and significantly reduces the tedium involved in verifying such designs. The tool is presented and how it was used to specify and verify the interactive consistency circuit is described