A 112 Gb/s Radiation-Hardened Mid-Board Optical Transceiver in 130-nm SiGe BiCMOS for Intra-Satellite Links

We report the design of a 112 Gb/s radiation-hardened (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises a vertical-cavity surface-emitting laser (VCSEL) driver and transimpedance amplifier (TIA) integrated circuits (ICs) with four channels per die, which are adapted for a flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130 nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/fMAX values of up to 250/340 GHz. Besides hardening by technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELTs) and digital logic cells. We report design features of the ICs and the module, and provide performance data from post-layout simulations. We present radiation evaluation data on analog devices and digital cells, which indicate that the transceiver ICs will reliably operate at typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites

The H2020-SPACE-SIPHODIAS project: Space-grade optoelectronic interfaces for photonic digital and analogue very-high-throughput satellite payloads

The EU-SIPhoDiAS project deals with the development of critical photonic building blocks needed for high-performance and low size, weight, and power (SWaP) photonics-enabled Very High Throughput Satellites (VHTS). In this presentation, we report on the design and fabrication activities during the first year of the project concerning the targeted family of digital and microwave photonic components. This effort aims to demonstrate components of enhanced reliability at technology readiness level (TRL) 7. Specifically, with respect to microwave photonic links, we report: (i) the design of Ka and Q-bands analogue photodetectors that will be assembled in compact packages, allowing for very high bandwidth per unit area and (ii) on the design of compact V-band GaAs electro-optic modulator arrays, which use a folded-path optical configuration to manage all fiber interfaces packaged opposite direct in-line RF feeds for ease of board layouts and mass/size benefits. With respect to digital links, we report on the development of 100 Gb/s (4 x 25 Gb/s) digital optical transceiver sub-assemblies developed using flip-chip mounting of electronic and opto-parts on a high-reliability borosilicate substrate. The transceiver chipset developed specifically for this project refers to fully-custom 25 Gb/s radiation hard (RH) VCSEL driver and TIA ICs designed in IHP’s 130 nm SiGe BiCMOS Rad-Hard process

Continuous-time digital processing techniques applied to channnel equalization for low-power millimeter-wave communications

Les récepteurs pour les communications sans fil très haut débit à 60 GHz tirent profit des innovations des liens filaires afin de réduire le budget de puissance, ce qui permettra l'intégration de la prochaine génération des terminaux portables sans fil. L’implémentation d’un égaliseur de canal à décision rétroactive, utilisant des signaux mixtes, est proposé pour diminuer la consommation globale du système. Dans ce mémoire, la réduction de consommation est atteinte par l'élimination de l'horloge du chemin de rétroaction de l’égaliseur. Inspiré par des récents développements en traitement des signaux numériques en temps continu, une ligne à retard numérique est aussi introduite. Le système conçu vise à atténuer les effets causés par les réflexions du signal dans des contextes de transmission en contact visuel entre le transmetteur et le récepteur. Les résultats théoriques montrent ainsi une consommation dépendante de la réalisation du canal. En outre, un élément de délai numérique programmable est proposé en tant qu’élément granulaire de la ligne à retard, en exploitant la polarisation de substrat des transistors, afin d’atteindre un réglage des délais extrêmement fin. Des démonstrateurs sur Silicium ont été fabriqués et caractérisés en technologie 28 nm FDSOI (Fully Depleted Silicon Over Insulator) pour démontrer les concepts proposés dans cette thèse.Receivers for 60GHz wireless communications have been profiting from innovation in wired links in order to meet a power budget that will enable integration in next‐generation high-speed portable wireless terminals. Mixed‐signal implementations of the Decision Feedback Equalizer (DFE) have been proposed to alleviate overall system consumption. In this thesis, power minimization is pursued by removing the clock from the feedback path of the DFE. Inspired by recent developments in Continuous‐Time Digital Signal Processing, a continuous‐time digital delay line is used. The design aims at mitigating wireless channel impairments caused by signal reflections in typical Line‐of‐Sight, indoors deployment conditions. The system is shown theoretically to achieve channel‐dependent power consumption within acceptable Bit Error Rate performance for decoding. Moreover, a programmable digital delay element is proposed as the granular element of the delay line that exploits body biasing to achieve a coarse/fine functionality. Prototype DFE and delay lines have been fabricated and characterized in 28nm Fully Depleted Silicon Over Insulator technology (FDSOI)

Subthreshold neuromorphic devices for spiking neural networks applied to embedded A.I

International audienceEnergy autonomy is one of the major challenges of embedded Artificial Intelligence. Among the candidate technologies likely to take up such a challenge, spiking neural networks are the most promising because of both their spatio-temporal and sparse representation of the information. In this context, this paper presents a neuromorphic approach based on an industrial CMOS technology and adopting an entirely subthreshold mode of operation (supply voltage VDD lower than the MOSFET threshold voltage). The detailed topologies of fabricated artificial neurons and synapses are presented as well as experimental results, validating an energy consumption of the order of a few femto-Joules per spike. Also, an arrangement of neurons and synapses is proposed to qualify experimentally this subthreshold approach in the perspective of highly energy efficient spiking neural networks

Sub-0.3V CMOS neuromorphic technology and its potential application

oral special sessionInternational audienceThe aim of this paper is to present a sub-0.3 V neuromorphic technology developed for spiking neural network design and its potential application. The main properties of the developed ultra low power (ULP) artificial neuron are first recalled. A description of ULP synapses follows that includes the plasticity scheme. The neuromorphic toolbox is then used to design a basic circuit allowing oriented edges classification. The circuit is made of 40 neurons and 108 plastic synapses, its consumed silicon core area is 0.025 mm 2 and the overall power consumption of 5 nW. Finally, the deployment of the technology within an industrial context to fabricate highly energy efficient Spike-based visual sensor is discussed

Open problems in brain-emulating hardware: [Invited]

International audienc

Open problems in brain-emulating hardware: [Invited]

International audienc

A 112 Gb/s radiation-hard mid-board optical transceiver in 130 nm SiGe BiCMOS for intra-satellite links

We report the design of 112 Gb/s radiation-hard (RH) optical transceiver applicable to intra-satellite optical interconnects. The transceiver chipset comprises of VCSEL driver and transimpedance amplifier (TIA) ICs integrated with four channels per die, which are adapted for flip-chip assembly into a mid-board optics (MBO) optical transceiver module. The ICs are designed in the IHP 130nm SiGe BiCMOS process (SG13RH) leveraging proven robustness in radiation environments and high-speed performance featuring bipolar transistors (HBTs) with fT/ fMAX values of up to 250/340 GHz. Besides hardening-by-technology, radiation-hardened-by-design (RHBD) components are used, including enclosed layout transistors (ELT) and digital logic cells. We report design features of the ICs and module and provide performance data from post-layout simulations. We present radiation evaluation data on the analogue devices and digital cells, which indicate that the transceiver ICs would operate under typical total ionizing dose (TID) levels and single event latch-up thresholds found in geostationary satellites