A NOVEL DOUBLE GATE FINFET TRANSISTOR: OPTIMIZED POWER AND PERFORMANCE ANALYSIS FOR EMERGING NANOTECHNOLOGIES

Abstract—FinFET technology has been proposed as a promising alternative for deep sub-micron CMOS technology,because of its superior device performance, scalability, lower leakage power consumption and cost-effective fabricationprocess. Fin-type field-effect transistors (FinFETs) are capable substitutes for bulk CMOS at the nano-scale. Previous workshave studied the performance or power advantages of FinFET circuits over bulk CMOS circuits. This paper elucidates thedependability analysis of Average power, Leakage power, Leakage current and Delay of AND gate using double gateFinFET. Our experiments compare FinFET circuits at different voltages at 45 nm technology in virtuoso tool of cadence,showing that DG FinFET circuits have better dependability and scalability.Keywords—double gate FinFET; fin width; low power circuit; device analysi

Comparative Analysis of Self-Controllable Voltage Level (SVL) and Stacking Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45Nanometer Regime

Abstract Today leakage power has become an increasingly major issue in low power VLSI design. With the most important element of leakage, the sub-threshold current, exponentially increasing with decreasing device dimension, leakage commands associate ever increasing share in the processor power consumption. In this paper two techniques such as transistor stacking and self controllable voltage-level (SVL) circuit for reducing leakage power in sequential circuits are proposed. This work analysis the power and delay of three different types of D Flip-flops using pass transistors logic, transmission gates and gate diffusion input (GDI) cmos design style. All the circuit parameters are simulated with and without the application of leakage reduction techniques. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameter

Modeling and Simulation of D Flip-Flop using MTCMOS Technique

In present CMOS circuits, the power dissipation caused by leakage current cannot be neglected any more. The current use of multi-Vt to control leakage power targets combinational gates, even though sequential elements such as flip flops also contribute appreciable leakage. In this paper low power, high speed design of D flip flop is enumerated. Numerous techniques are utilized to minimize sub-threshold leakage power as well as the power consumption of the CMOS circuits.  The proposed circuit in this paper shows a design for D flip flop to increase overall speed of the circuit as compared to other circuits by using minimum number of transistors to achieve lowest power consumption. This paper proposes four leakage reduction techniques such as leakage feedback; gate-length biasing, dual threshold techniques and MTCMOS for use in D flip flop. This work analyses the leakage- current and power of different implementation of D flip flop using transmission gate. All the designs are simulated using Cadence in 45nm process technology. Simulation result shows that the proposed MTCMOS based D flip flop has the least leakage power dissipation

Power delay optimization of nanoscale 4×1 multiplexer using CMOS based voltage doubler circuit

This paper represents a low leakage, highly efficient and delay improved 4×1 MUX with MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration with nanoscale structure. The unique newly designed voltage doubler circuit is implemented as an additional circuit at the output of the implemented proposed design to step-up the voltage. It means that the output peak voltage is doubled due to the transient of both positive and negative cycles. This stepped-up voltage may be exploited as a stabilized supply for specific applications. The voltage doubler circuit is not enough to improve the overall performance of proposed 4×1 MUX design. In order to integrate the optimization criterion of leakage power and delay performance, the voltage doubler circuit is utilized along with the MOS configuration of augmented sleep transistors. To minimize the parameter of leakage power dissipation the MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration is introduced. This will mitigate the redundant unused leakage power dissipation of the circuit. This additional circuitry brings out the aspired level of output voltage for the proposed and implemented 4×1 MUX with better performance parameters. The whole simulation has been done for the 45 nm technology. It is finally summarized that the leakage power dissipation is minimized up to 55% just around and the delay performance is also improved up to a desired level due to the utilization of MOS based voltage doubler circuit with the MOS configuration of augmented sleep transistors. In this paper, different combinations of MOS based augmented voltage doubler circuit implemented at the output of 4×1 MUX are represented

International Symposium on Computing and Network Sustainability

The book is compilation of technical papers presented at International Research Symposium on Computing and Network Sustainability (IRSCNS 2016) held in Goa, India on 1st and 2nd July 2016. The areas covered in the book are sustainable computing and security, sustainable systems and technologies, sustainable methodologies and applications, sustainable networks applications and solutions, user-centered services and systems and mobile data management. The novel and recent technologies presented in the book are going to be helpful for researchers and industries in their advanced works

Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage Vth, channel length L and gate oxide thickness tox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology