International Journal of Advances in Engineering Sciences

    A Parametric Study of Temperature Dependent Properties Influenced due to Transient Temperature Field Developed in Arc Welded Steel Butt Joints

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    This article describes a detailed study of variation of temperature dependent properties developed due to the transient temperature field involved in making arc welded butt joints. Four rectangular plate butt joints of AISI 1040 material, prepared at four different heat inputs with constant welding velocity. Experimentally temperature has been measured at predefined locations of the plate during welding by mounting of thermocouples. The heat transfer coefficient based on experimental results has been compared with established Vinokurov’s empirical correlation. Based on critical plate thickness, cooling rate has been studied to visualize the variation with heat input. It was found out that convection - radiation coupled heat transfer has dominant effect in the region of Heat Affected Zone (HAZ), near the fusion boundary (300°C-900°C) and radiation heat transfer plays a dominant role in heat loss due to moving point heat source

    CMOS Voltage Level-Up Shifter – A Review

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    This paper presents a review on variousCMOS voltage level shifters. A voltage level-shiftershifts the level of output voltage from a digital circuit.Level Shifter circuits are compared in terms of outputvoltage level, power consumption and delay. The inputvoltage is set to 1.6V. Simulations have been carriedout in SPICE based on TSMC 0.18μm CMOStechnology

    Qualitative Perspective of cohesion and coupling to optimize the refactored code

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    In order to improve the design of object orientedsoftware internally, key design principles are to be applied byrefactoring the existing code [1] partially delivering thefulfillment of the concept low coupling and high cohesion withbetter adherence to open closed principle. The open closedprinciple is extended by applying changes in internalstructure without affecting external behavior of objectoriented software. The refactoring technique is useful toadhere to open closed principl

    Analysis of Single-Event Upsets in Phase-Locked Loops

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    Exploration of space provides us with usefulinformation about the universe. Understanding the number ofissues and solving them lead to progress in this field. The sun ismajor source of radiation, thus the radiation experienced by thespace-craft in the outer space is one of the issue. The electroniccircuitry on-board the space-crafts are exposed to theseradiations and may result in reduction of the lifetime of thespace-crafts and even cause failure. Thus for successful and safeexploration of space it is necessary to analyze and understand the effects of radiation on any electronics circuitry. One of the main integral parts of many electronic systems is a phase-lockedloop(PLL) which is widely used in commercial and spacedeployedelectronic system to reduce phase delay associated withdistribution of clock signal. Single event upsets (SEUs) have been a growing concern in modern integrated circuits (ICs) whereincreased susceptibilities to SEUs have been reported as devicefeature sizes decrease and operating frequencies increase [1].Thus analyzing the effects of single event transients (SET) in PLLis important for all these applications. This paper summarizeseffects of radiation on different blocks in PL

    An Experimental Study on Open Sun Drying of Vermicelli

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    In this research paper, an attempt has been made to determine the convective heat transfer coefficients of vermicelli for different thicknesses under open sun drying mode. Various experiments were conducted in the months of March and April 2012 for open sun drying of vermicelli in the climatic conditions of Rohtak (28o 40’: 29 05’N 76o 13’: 76o 51’E). Experimental data were used to evaluate the values of constants (C and n) in the Nusselt number expression by using linear regression analysis and consequently convective heat transfer coefficients were determined. The average values of convective heat transfer coefficients were found to be 5.61 W/m2 oC and 4.13 W/m2 oC for vermicelli of diameters 2 mm and 1.25 mm respectively. The experimental errors in terms of percent uncertainty have also been evaluated

    Comparison of Wavelet Transform and Fourier Transform based methods of Phasor Estimation for Numerical Relaying

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    Estimation of fundamental frequency component of current and/or voltage signals is essential for relaying decision in most of the numerical algorithms used for the protection of power system components. Modern numerical relays generally use discrete Fourier transform for extracting the fundamental component from the post fault signals consisting of fundamental as well as non-fundamental frequency signals. With the advent of wavelet analysis, many researchers used wavelet analysis for the phasor estimation with the claims of better performance. The paper compares the performance of discrete wavelet transform method with discrete Fourier transform method for phasor estimation, considering the effect of decaying dc offset. MATLAB software was used for programming and simulation

    Comparison of Musical Pitch Analysis Between LPC and CELP

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    Currently, numerous voice coding techniques are used for voice processing purposes. Each type of these techniques has its own strengths and weaknesses. However, all the coding techniques fail to deliver a satisfactory performance when it comes to music processing. In this paper, we have worked with two very popular and contemporary voice coding techniques: Linear Prediction Coding (LPC) and Code Excited Linear Prediction Coding (CELP). This paper focuses on the implementation and simulation of both these state of the art coding techniques. The paper also focuses on the determination of which technique gives better performance for music synthesis. Finally, comparative study of the performance through pitch analysis have been made and proposed the technique which is better applicable for musical voice synthes

    A fresh loom for Multilevel feedback Queue scheduling Algorithm

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    CPU scheduling is a vital phenomenon of operating system. At present, numerous CPU scheduling algorithms are existing like FCFS(First come first serve), SJF (shortest job first),SRTF( Shortest remaining time first) , Priority Scheduling,(RR)Round Robin scheduling , MLQ( multilevel queue). Efficiency and performance are not remaining satisfactory of these algorithms. MLFQ( Multilevel feedback queue) be one of most potential strategies, for CPU scheduling .It  is further extension of multi-level queue scheduling algorithm while multilevel queue scheduling is results of combination of basic scheduling algorithms such as FCFS and RR scheduling algorithm. Therefore, research on these algorithms remains continuing till today. This paper, suggested a novel approach which will improve the performance of MLFQ (CPU) scheduling algorithm

    Use of Active Rules and Genetic Algorithm to Generate the Automatic Time-Table

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    This document proposes an optimized techniqueto automate time table generation system. Time tablegeneration system involves various challenging constraintsof resources including faculties, rooms, time slots etc. Theproposed technique filters out the best of active rules andGenetic algorithm to generate the optimized solution.Genetic Algorithm and Active Rules together form acomplete sphere for developing a system, which needs tosatisfy various constraints.Active Rules provide “event-condition-action†model forthe implementation of any rule based system. In geneticalgorithm every individual are characterized by a fitnessfunction. After analysis if there is higher fitness then itmeans better solution and then after based on their fitness,parents are selected to reproduce offspring for a newgeneration where fitter individuals have more chance toreproduce. The objective of the work is to create a modelused to generate the acceptable schedule using probabilisticoperators

    Efficient FPGA Based Bidirectional Network on Chip Router throgh Virtual Channel Regulator

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    Fundamental unit of building a Network on Chipis the router; it directs the packets according to a routingalgorithm to the desired host. Both NoC performance andenergy budget depend heavily on the routers' bufferresources. This paper introduces a novel BidirectionalNetwork on chip router with unified buffer structure, calledthe dynamic Virtual Channel Regulator, which dynamicallyallocates Virtual Channels (VC) and buffer resourcesaccording to network traffic conditions. In this study, weanalyse the move towards Networks-on-Chips router froman area and power perspective by accurately modeling aBidirectional Network-on-chip router through VirtualChannel Regulator in FPGA. Accurate speed, area andpower metrics are also reported for the networks router,which will allow a more complete comparison to be madeacross the NoC architectural router space considered. Theproposed architecture of BiNoC router is simulated in XilinxISE 9.1i software. We designed a router with scalabilityfeature which is synthesized in models of Virtex-II XC2VP30FPGA infrastructures. The source code is written in VHDL.In addition, the proposed router uses low resource utilizationpercentage of FPGA. From the implementation results, theproposed router is operated with higher speed, area in termsof slices reduced by 38.55% and the LUTs reduced by44.59
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