178 research outputs found
Are spin junction transistors suitable for signal processing?
A number of spintronic junction transistors, that exploit the spin degree of
freedom of an electron in addition to the charge degree of freedom, have been
proposed to provide simultaneous non-volatile storage and signal processing
functionality. Here, we show that some of these transistors unfortunately may
not have sufficient voltage and current gains for signal processing. This is
primarily because of a large output ac conductance and poor isolation between
input and output. The latter also hinders unidirectional propagation of logic
signal from the input of a logic gate to the output. Other versions of these
transistors appear to have better gain and isolation, but not better than those
of a conventional transistor. Therefore, these devices may not improve
state-of-the-art signal processing capability, although they may provide
additional functionality by offering non-volatile storage. They may also have
niche applications in non-linear circuits
Architectures for a quantum random access memory
A random access memory, or RAM, is a device that, when interrogated, returns
the content of a memory location in a memory array. A quantum RAM, or qRAM,
allows one to access superpositions of memory sites, which may contain either
quantum or classical information. RAMs and qRAMs with n-bit addresses can
access 2^n memory sites. Any design for a RAM or qRAM then requires O(2^n)
two-bit logic gates. At first sight this requirement might seem to make large
scale quantum versions of such devices impractical, due to the difficulty of
constructing and operating coherent devices with large numbers of quantum logic
gates. Here we analyze two different RAM architectures (the conventional fanout
and the "bucket brigade") and propose some proof-of-principle implementations
which show that in principle only O(n) two-qubit physical interactions need
take place during each qRAM call. That is, although a qRAM needs O(2^n) quantum
logic gates, only O(n) need to be activated during a memory call. The resulting
decrease in resources could give rise to the construction of large qRAMs that
could operate without the need for extensive quantum error correction.Comment: 10 pages, 7 figures. Updated version includes the answers to the
Refere
Nanofilters for Optical Nanocircuits
We theoretically and numerically study the design of optical 'lumped'
nanofiltering devices in the framework of our recently proposed paradigm for
optical nanocircuits. In particular, we present the design of basic filtering
elements, such as low-pass, band-pass, stop-band and high-pass 'lumped'
nanofilters, for use in optical nanocircuits together with more complex
designs, such as multi-zero or multi-pole nanofilters, to work at THz, infrared
and optical frequencies. Following the nanocircuit theory, we show how it is
possible to design such complex frequency responses by simple rules, similar to
RF circuit design, and we compare the frequency response of these optical
nanofilters with classic filters in RF circuits. These results may provide a
theoretical foundation for fabricating nanofilters in optical lumped
nanocircuit devices.Comment: 34 pages, 14 figure
On the robustness of bucket brigade quantum RAM
We study the robustness of the bucket brigade quantum random access memory
model introduced by Giovannetti, Lloyd, and Maccone [Phys. Rev. Lett. 100,
160501 (2008)]. Due to a result of Regev and Schiff [ICALP '08 pp. 773], we
show that for a class of error models the error rate per gate in the bucket
brigade quantum memory has to be of order (where is the
size of the memory) whenever the memory is used as an oracle for the quantum
searching problem. We conjecture that this is the case for any realistic error
model that will be encountered in practice, and that for algorithms with
super-polynomially many oracle queries the error rate must be
super-polynomially small, which further motivates the need for quantum error
correction. By contrast, for algorithms such as matrix inversion [Phys. Rev.
Lett. 103, 150502 (2009)] or quantum machine learning [Phys. Rev. Lett. 113,
130503 (2014)] that only require a polynomial number of queries, the error rate
only needs to be polynomially small and quantum error correction may not be
required. We introduce a circuit model for the quantum bucket brigade
architecture and argue that quantum error correction for the circuit causes the
quantum bucket brigade architecture to lose its primary advantage of a small
number of "active" gates, since all components have to be actively error
corrected.Comment: Replaced with the published version. 13 pages, 9 figure
On ADE Quiver Models and F-Theory Compactification
Based on mirror symmetry, we discuss geometric engineering of N=1 ADE quiver
models from F-theory compactifications on elliptic K3 surfaces fibered over
certain four-dimensional base spaces. The latter are constructed as
intersecting 4-cycles according to ADE Dynkin diagrams, thereby mimicking the
construction of Calabi-Yau threefolds used in geometric engineering in type II
superstring theory. Matter is incorporated by considering D7-branes wrapping
these 4-cycles. Using a geometric procedure referred to as folding, we discuss
how the corresponding physics can be converted into a scenario with D5-branes
wrapping 2-cycles of ALE spaces.Comment: 21 pages, Latex, minor change
Electron Spin for Classical Information Processing: A Brief Survey of Spin-Based Logic Devices, Gates and Circuits
In electronics, information has been traditionally stored, processed and
communicated using an electron's charge. This paradigm is increasingly turning
out to be energy-inefficient, because movement of charge within an
information-processing device invariably causes current flow and an associated
dissipation. Replacing charge with the "spin" of an electron to encode
information may eliminate much of this dissipation and lead to more
energy-efficient "green electronics". This realization has spurred significant
research in spintronic devices and circuits where spin either directly acts as
the physical variable for hosting information or augments the role of charge.
In this review article, we discuss and elucidate some of these ideas, and
highlight their strengths and weaknesses. Many of them can potentially reduce
energy dissipation significantly, but unfortunately are error-prone and
unreliable. Moreover, there are serious obstacles to their technological
implementation that may be difficult to overcome in the near term.
This review addresses three constructs: (1) single devices or binary switches
that can be constituents of Boolean logic gates for digital information
processing, (2) complete gates that are capable of performing specific Boolean
logic operations, and (3) combinational circuits or architectures (equivalent
to many gates working in unison) that are capable of performing universal
computation.Comment: Topical Revie
Lagrange formalism of memory circuit elements: classical and quantum formulations
The general Lagrange-Euler formalism for the three memory circuit elements,
namely, memristive, memcapacitive, and meminductive systems, is introduced. In
addition, {\it mutual meminductance}, i.e. mutual inductance with a state
depending on the past evolution of the system, is defined. The Lagrange-Euler
formalism for a general circuit network, the related work-energy theorem, and
the generalized Joule's first law are also obtained. Examples of this formalism
applied to specific circuits are provided, and the corresponding Hamiltonian
and its quantization for the case of non-dissipative elements are discussed.
The notion of {\it memory quanta}, the quantum excitations of the memory
degrees of freedom, is presented. Specific examples are used to show that the
coupling between these quanta and the well-known charge quanta can lead to a
splitting of degenerate levels and to other experimentally observable quantum
effects
Modelling amorphous computations with transcription networks
The power of electronic computation is due in part to the development of modular gate structures that can be coupled to carry out sophisticated logical operations and whose performance can be readily modelled. However, the equivalences between electronic and biochemical operations are far from obvious. In order to help cross between these disciplines, we develop an analogy between complementary metal oxide semiconductor and transcriptional logic gates. We surmise that these transcriptional logic gates might prove to be useful in amorphous computations and model the abilities of immobilized gates to form patterns. Finally, to begin to implement these computations, we design unique hairpin transcriptional gates and then characterize these gates in a binary latch similar to that already demonstrated by Kim et al. (Kim, White & Winfree 2006 Mol. Syst. Biol. 2, 68 (doi:10.1038/msb4100099)). The hairpin transcriptional gates are uniquely suited to the design of a complementary NAND gate that can serve as an underlying basis of molecular computing that can output matter rather than electronic information
Mega-exposição dos Açores em S. Paulo, Brasil
Na qualidade de Diretora Regional das Comunidades, fomos responsável pela redação dos artigos e coordenação da página "Comunidades", integrada no jornal Açoriano Oriental, servindo a mesma para a divulgação das atividades realizadas pela Direção Regional Das Comunidades do Governo dos Açores.Se existe manifestação religiosa que possa caracterizar o povo açoriano, nas ilhas e sua diáspora, o culto ao Divino Espírito Santo, é, sem dúvida, o que reúne a primazia. Consciente de que as Festas ao Divino são fator de união entre todos os açorianos pelo mundo e motivo de interesse e estudo por parte de académicos, a DRC encontra-se a organizar o V Congresso Internacional do Culto do Divino Espírito Santo, que se vai realizar, em Maio, na Terceira. Contamos com a presença de largas dezenas de açorianos e açordescendentes que representarão as nossas comunidades. [...]
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