Modeling of Wearout, Leakage, and Breakdown of Gate Dielectrics

Abstract We present a set of models for the simulation of gate dielectric wearout, leakage, and breakdown. Wearout is caused by the leakage-induced creation of neutral defects at random positions in the dielectric layer, which, if occupied, degrade the threshold voltage of the device. Leakage is due to direct and trap-assisted tunneling through these defects. Finally, gate dielectric breakdown is triggered by the formation of a conductive path through the insulator. To allow the trap characterization and for the simulation of fast transients the modeling of trap charging and decharging processes is outlined. The model has been implemented into a threedimensional device simulator and is used for the characterization of ZrO 2 -based dielectrics and for the study of gate leakage and wearout effects in standard CMOS inverter circuits

Electromigration Induced Failure of Solder Bumps and the Role of IMC

Abstract Characteristic for solder bumps is that during technology processing and usage their material composition changes. We present a model for describing the growth of an intermetallic compound inside a solder bump under the influence of electromigration. Simulation results based on our model are discussed in conjunction with corresponding experimental findings

Mobility Modeling in Advanced MOSFETs with Ultra-Thin Silicon Body under Stress

Mobility in advanced MOSFETs with strained ultra-thin silicon body is investigated. We use a two-band k·p model to describe the subband structure in strained silicon thin films. The model provides the dependence of the conductivity effective mass on strain and film thickness. The conductivity mass decreases along tensile stess in [110] direction applied to a (001) silicon film. This conductivity mass decrease ensures the mobility enhancement in MOSFETs even with extremely thin silicon films. The two-band k·p model also describes the non-parabolicity dependence on film thickness and on strain. Dependence of the non-parabolicity parameter on both film thickness and strain reduces the mobility enhancement due to the conductivity mass modification, especially at higher strain values

Electrical plasmon detection in graphene waveguides

We present a simple device architecture that allows all-electrical detection of plasmons in a graphene waveguide. The key principle of our electrical plasmon detection scheme is the non-linear nature of the hydrodynamic equations of motion that describe transport in graphene at room temperature and in a wide range of carrier densities. These non-linearities yield a dc voltage in response to the oscillating field of a propagating plasmon. For illustrative purposes, we calculate the dc voltage arising from the propagation of the lowest-energy modes in a fully analytical fashion. Our device architecture for all-electrical plasmon detection paves the way for the integration of graphene plasmonic waveguides in electronic circuits.Comment: 9 pages, 3 figure

Emerging memory technologies: trends, challenges, and modeling methods”,

a b s t r a c t In this paper we analyze the possibility of creating a universal non-volatile memory in a near future. Unlike DRAM and flash memories a new universal memory should not require electric charge storing, but alternative principles of information storage. For the successful application a new universal memory must also exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, and a simple structure. Several alternative principles of information storage are reviewed. We discuss different memory technologies based on these principles, highlight the most promising candidates for future universal memory, make an overview of the current state-of-the-art of these technologies, and outline future trends and possible challenges by modeling the switching process

Reduction of the Dark-Current in Carbon Nanotube Photo-Detectors

Abstract-Carbon nanotubes have been considered in recent years for future opto-electronic applications because of their direct band-gap and the tunability of the band-gap with the CNT diameter. The performance of infra-red photo-detectors based on carbon nanotube field-effect transistors is analyzed, using the non-equilibrium Green's function formalism. The relatively low ratio of the photo-current to the dark current limits the performance of such devices. We show that by employing a double gate structure this ratio can be significantly increased. Carbon nanotubes (CNTs) have been extensively studied in recent years due to their exceptional electronic, optoelectronic, and mechanical properties. CNTs can be considered as a graphene sheet which has been wrapped into a tube. The way the graphene sheet is wrapped is represented by a pair of indices (n, m) called the chiral vector. The integers n and m denote the number of unit vectors along two directions in the honeycomb crystal lattice of graphene. If m = 0, the CNT is called zigzag. If n = m, the CNT is called armchair. Otherwise, it is called chiral. CNTs with n−m = 3 are metals, otherwise they are semiconductors. Semiconducting CNTs can be used as channels for transistors. Depending on the work function difference between the metal contact and the CNT, carriers at the metal-CNT interface encounter different barrier heights. Fabrication of devices with positive [1] and zero Some of the interesting electronic properties of CNTs are quasi-ballistic carrier transport [2], suppression of shortchannel effects due to one-dimensional electron transport IR photo detectors based on carbon nanotube field effect transistors (CNT-FETs) have been reported i

Industrial Application of Heterostructure Device Simulation,”

Abstract-We give an overview of the state-of-theart of heterostructure RF-device simulation for industrial application based on III-V compound semiconductors. Results for Heterostructure Bipolar Transistors (HBTs) and for High Electron Mobility Transistors (HEMTs) are presented in good agreement with measured data of industrially relevant devices

An event bias technique for Monte Carlo device simulation

Abstract In Monte Carlo (MC) simulations of semiconductor devices it is necessary to enhance the statistics in sparsely populated regions of interest. In this work the Monte Carlo method for stationary carrier transport, known as the Single-Particle MC method, is considered. It gives a solution to the stationary boundary value problem defined by the semi-classical Boltzmann equation (BE). Using a formal approach which employs the integral form of the problem and the Neumann series expansion of the solution, the Single-Particle MC method is derived in a formal way. The independent, identically distributed random variables of the simulated process are identified. Estimates of the stochastic error are given. Furthermore, the extension of the MC estimators to the case of biased events is derived. An event bias technique for particle transport across an energy barrier is developed and simulation results are discussed

Stochastic Model of the Resistive Switching Mechanism in Bipolar Resistive Random Access Memory: Monte Carlo Simulations”,

Memory is an indispensible important component of any modern integrated circuit. While MOSFET scaling has reached tremendous advances, semiconductor memory scaling is lagging behind. Standard DRAM cell scaling is hampered by the presence of a capacitor which is difficult to reduce in size. Z-RAM uses a bitcell composed of a single transistor without a capacitor (1T/0C) ("Z" stands for Zero capacitor), unlike traditional one transistor plus one capacitor (1T/1C) DRAM bitcells. The advanced Z-RAM bitcells built on a multiple-gate MOSFET (MuGFET), where the parasitic bipolar transistor [1] is utilized, which exists in SOI MOSFETs. The current flows through the body of the structure and is thus much increased. The majority carriers generated due to impact ionization are stored under the gates. The stored charge offers a good control over the current. The threshold voltage is modified by the stored charge guaranteeing two states of the bipolar transistor with high and low current, correspondingly. The stored charge for the two states is shown in Charge-based memories including flash are, however, gradually approaching the physical limits of scalability, and the search for new nonvolatile memory concepts has significantly accelerated. Several new memory structures as potential substitutes of the flash memory were invented and developed: a technology of phase change RAM (PCRAM), spin transfer torque RAM (STTRAM), carbon nanotube RAM (NRAM), copper bridge RAM (CBRAM), racetrack memory, and resistive RAM (RRAM). A new type of nonvolatile memory must exhibit low operating voltages, low power consumption, high operation speed, long retention time, high endurance, simple structure, and small size. One of the most promising candidates for future universal memory is the resistive random access memory (RRAM) The spin transfer torque random access memory (STTRAM) is another promising candidate for future universal memory. The reduction of the current density required for switching and the increase of the switching speed are among the most important challenges in this area. A decrease in the critical current density for the penta-layer magnetic tunnel junction was reported i