Optimization of process parameter variation in double-gate FinFET model using various statistical methods

Double-gate FinFET is identified as a prospect in fulfilling the demands required in replacing the current conventional planar MOSFETs due to several advantages. Specifically in its scalability, reduced leakage current, high drive current, with steep subthreshold swing, subsequently improving the ION/IOFF ratio, thus reducing the power consumption of the device. The susceptibility towards the electrical performance of the device is exposed due to the process parameter variations from the device miniaturization. This research work is aimed towards optimizing the process parameter variation towards the device characteristics with several appropriate statistical methods used. Taguchi statistical method, the Taguchi-based Grey Relational Analysis (GRA), the 2k-factorial method, and the Response surface method-central composite design (RSM-CCD) have all been utilized to analyze the performance of the device. ATHENA module of Silvaco TCAD is utilized in this simulation-based fabrication The threshold voltage (VTH), drive current (ION), leakage current (IOFF) and subthreshold swing (SS) ramifications towards the adjustment of six process parameter that include polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose and VTH doping tilt is studied. The effect of the said process parameter variations were analysed with the utilization of L25 orthogonal array (OA), main effects, signal-to noise ratio (SNR) and analysis of variance (ANOVA) for the Taguchi statistical method, the Taguchi-based GRA and the RSM-CCD. Meanwhile the L32 OA is utilized in the 2k-factorial method where 1/8 fraction design of experiment is used with each requires 64, 32, 16 and eight experiment runs respectively. This has made the L32 the nearest available in the 2kfactorial method to the L25 used in other statistical methods. The performance of the device is analyzed through the ION values along with ION/IOFF ratio amongst the statistical methods used. The combination of Taguchi method and GRA is introduced to overcome the limitation of a standalone Taguchi method that can solve only a single response at a time into multi-response optimization for the 16 nm gate length of double-gate FinFET. The Taguchi-based GRA showcases the best improvements with 47.79% for the ION/IOFF ratio as opposed to 45.39%, 20.54% and 23.01% for the Taguchi method, 2k-factorial and RSMCCD respectively, with ION at 1656.27 ȝA/ȝm for the TagXchi based GRA. Meanwhile, the IOFF, SS and ION/IOFF ratio optimized at 34.498 pA/ȝm, 96.743 mV/decade, and 48.0113 M, respectively. The process parameters of 16 nm gate length double gate FinFETs were successfully optimized by using the L25 OA of Taguchi based GRA. Following that, a nominal VTH, a high ION and a low IOFF characteristics were all attained. These proved that the multi-response characteristics of the device can be optimized simultaneously through the implementation of the L25 OA of Taguchi based GRA. That said, the VTH, ION and IOFF value for both devices meet the International Technology Roadmap Semiconductor (ITRS) 2013 prediction for high performance and low power logic multi-gate technology

Optimal Design Of Junctionless Double Gate Vertical MOSFET Using Hybrid Taguchi-GRA With ANN Prediction

Random parameter variations have been an influential factor that deciding the performance of a metal-oxide-semiconductor field effect transistor (MOSFET), especially in nano-scale regime. Thus, controlling the variation of those parameters becomes extremely crucial in order to attain an acceptable performance of an ultra-small MOSFET. This paper proposes an approach to optimally design a n-type junctionless double-gate vertical MOSFET (nJLDGVM) via hybrid Taguchi-grey relational analysis (GRA) with artificial neural networks (ANN) prediction. The device is designed using a combination of 2-D simulation tools (Silvaco) and hybrid Taguchi-GRA with a well-trained ANN prediction. The investigated device parameters consist of channel length (Lch), pillar thickness (Tp), channel doping (Nch) and source/drain doping (Nsd). The optimized design parameters of the device demonstrate a tolerable magnitude of on-state current (ION), off-state current (IOFF), on-off ratio, transconductance (gm), cut-off frequency (fT) and maximum oscillation frequency (fmax), measured at 2344.9 µA/µm, 2.53 pA/µm, 927 x 106, 4.78 mS/µm, 121.5 GHz and 2469 GHz respectively

Effect Of Channel Length Variation On Analog And RF Performance Of Junctionless Double Gate Vertical Mosfet

This paper investigates the effect of channel length (Lch) variation upon analogue and radio frequency (RF) performance of Junctionless Double Gate Vertical MOSFET (JLDGVM). The study has been performed under the fixed level of process parameters by considering the dependence of analogue and RF properties on the channel length. Furthermore, this paper aims to give a comprehensive insight on possible improvement in the performance of analogue and RF of the JLDGVM device. The structure and characteristics of the device are developed and extracted respectively via 2D TCAD simulation. The results show that both transconductance generation factor (TGF) and transconductance (gm) of the JLDGVM device are tremendously increased by 83% and 74% respectively as the scale of channel length is reduced from 12 nm to 9 nm. On the other hand, the unity gain cut-off frequency (fT) and the gain-band-width product (GBW) tremendously improved by ~93% and ~74% respectively as the channel length of the device is scaled from 12 nm to 9 nm

Predictive Analytics Of Cigs Solar Cell Using A Combinational Gra-Mlr-Ga Model

Thin-film Copper Indium Gallium Selenide (CIGS) solar cell is identified to be one of the promising structures to replace conventional silicon-based solar cell due to its lower cost and reduced thickness. Nevertheless, the impact of layer thickness and doping concentration of a window layer - Zinc oxide (ZnO), a buffer layer - Cadmium sulfide (Cds) and an absorber layer (CIGS) needs to be intelligently controlled for more balanced CIGS solar cell performances. Thus, this paper proposes a newly predictive analytics using a combination of Grey relational analysis (GRA), multiple linear regressions (MLR) and genetic algorithm (GA) to optimize the CIGS solar cell parameters for better device performances. The CIGS solar cell model is developed and simulated using solar cell capacitance simulator (SCAPS). The final results prove that the proposed combinational GRA-MLR-GA model has successfully optimized the CIGS solar cell parameters in which ZnO thickness (TZnO), Cds thickness (TCds), CIGS thickness (TCIGS) and CIGS doping concentration (NaCIGS) are predictively optimized to be 0.03 μm, 0.03μm, 2.86 μm and 9.937x1017 cm-3 respectively. The most optimum magnitudes for open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and power conversion efficiency (η) after the predictive analytics are measured at 0.8206 V, 32.419 mA/cm2, 83.23% and 22.14% reciprocally

Enhanced Performance Of 19 Single Gate MOSFET With High Permittivity Dielectric Material

In this research, the performance of the 19 nm single gate MOSFET is enhanced through the implementation of the high permittivity dielectric material. The MOSFET scaling trends necessities in device dimensions can be satisfied through the implementation of the high-K dielectric materials in place of the SiO2. Therefore, the 19 nm n-channel MOSFET device with different High-K dielectric materials are implemented and its performance improvement has also been analysed. Virtual fabrication is exercised through ATHENA module from Silvaco TCAD tool. Meanwhile, the device characteristic was utilized by using an ATLAS module. The aforementioned materials have also been simulated and compared with the conventional gate oxide SiO2 for the same structure. At the end, the results have proved that Titanium oxide (TiO2) device is the best dielectric material with a combination of metal gate Tungsten Silicides (WSix). The drive current (ION) of this device (WSix/TiO2) is 587.6 µA/um at 0.534 V of threshold voltage (VTH) as opposed to the targeted 0.530 V predicted, as well as a relatively low IOFF that is obtained at 1.92 pA/µm. This ION value meets the minimum requirement predicted by International Technology Roadmap for Semiconductor (ITRS) 2013 prediction for low performance (LP) technology

Comparative High-K Material Gate Spacer Impact In DG-FinFET Parameter Variations Between Two Structures

This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio), all three materials tested being S3N4, HfO2 and TiO2 increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (VTH) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO2 has improved by 12.94% after the alteration made in terms of the overall ION and IOFF performances through the ION/IOFF ratio value obtained, as well as meeting the required value for VTH obtained at 0.464V. The ION from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology. © 2019 Institute of Advanced Engineering and Science

Design Consideration And Impact Of Gate Length Variation On Junctionless Strained Double Gate MOSFET

Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (Lg) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (Lg) does contributes a significant impact on the drain current (ID), on-current (ION), off-current (IOFF), ION/IOFF ratio, subthreshold swing (SS) and transconductance (gm). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both ION and gm(max) are measured at 1680 µA/µm and 2.79 mS/µm respectively

Work Function Variations On Electrostatic And RF Performances Of JLSDGM Device

This paper offers a systematic analysis on the impact of work function (WF) variations on electrostatic and radio frequency (RF) performances of n-channel junctionless strained double gate (DG) (n-JLSDGM) metal oxide semiconductor field effect transistor (MOSFET). The study has been performed under othe constant level of design parameters that operates in saturation as a transconductance amplifier, considering the dependence of electrostatic and RF performance on the variation of WF. Furthermore, this paper aims to provide physical insight into the improved electrostatic and RF performances of the proposed n-JLSDGM device. The device layout and characteristics were designed and extracted respectively via a comprehensive 2-D simulation. Device performances such as on-state current (ION), off-state current (IOFF), on-off current ratio, subthreshold swing (SS), intrinsic capacitances, dynamic power dissipation (Pdyn), cut-off frequency (fT) and maximum oscillation frequency (fmax) are intensively investigated in conjunction with WF variations

Design Of Dual-Band Microstrip Patch Antenna With Right-Angle Triangular Aperture Slot For Energy Transfer Application

This work focusing on the dual‐band antenna design with rectifying circuit for energy transfer system technology for enhancement gain performance. The air gap technique is applied on this microstrip antenna design work to enhance the antenna gain. The work begins with designing and analyzing the antenna via the CST Microwave Studio software. After validation on acceptable performance in simulation side is obtained, the return loss, S11 of the antenna is measured using vector network analyzer equipment. The rectifier circuit is used to convert the captured signal to DC voltage. This projected dual‐band antenna has successfully accomplished the target on return loss of −44.707 dB and −32.163 dB at dual resonant frequencies for 1.8 GHz and 2.4 GHz, respectively. This proposed antenna design benefits in low cost fabrication and has achieved high gain of 6.31 dBi and 7.82 dBi for dual‐band functioning frequencies