Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery

The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling soft errors in the logic and memories that allow meeting the desired failures-in-time (FIT) target are key to keep harnessing the benefits of Moore's law. The failure to scale the soft error rate caused by particle strikes, may soon limit the total number of cores that one may have running at the same time. This paper proposes a light-weight and scalable architecture to eliminate silent data corruption errors (SDC) and detected unrecoverable errors (DUE) of a core. The architecture uses acoustic wave detectors for error detection. We propose to recover by confining the errors in the cache hierarchy, allowing us to deal with the relatively long detection latencies. Our results show that the proposed mechanism protects the whole core (logic, latches and memory arrays) incurring performance overhead as low as 0.60%. © 2014 IEEE.Peer ReviewedPostprint (author's final draft

Penelope: The NBTI-aware processor

Transistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias temperature instability) is one of the most important sources of failure affecting transistors. NBTI degrades PMOS transistors whenever the voltage at the gate is negative (logic inputPeer ReviewedPostprint (published version

Word learning:When associative learning meets social-pragmatic expectations

How we learn words has been a long-standing debate in psycholinguistics. Social-pragmatic approaches argue that word learning is underpinned by learners’ social-cognitive abilities, which allow them to determine the communicative intentions of their interlocutors. Associative learning approaches, on the other hand, suggest that word learning is possible thanks to the human ability to track the frequency of co-occurrences between a word and its referent. An intermediate approach is the communicative/intentional framework, which posits that the relationship between a word and its referent is mediated by the speaker's intention to refer to a particular (set of) object(s). The studies presented in this dissertation take this assumption as their theoretical backdrop and pose two general research questions: 1) to what extent do social-pragmatic cues affect cross-situational word learning?; and 2) when in time do social-pragmatic effects emerge when learning words across situations? We designed five experiments that tested the effects of speaker reliability and speaker informativeness on cross-situational word learning. The results neither support nor contradict the hypothesis that exposure to an unreliable speaker results in learning fewer words and/or relying on associative learning mechanisms. Furthermore, the evidence that participants were sensitive to speaker reliability was inconsistent. However, when the effect of speaker informativeness on word learning was measured over time (by means of an eye-tracker), the results showed that speaker informativeness influenced the initial selection of objects as potential referents. This finding highlights the importance of fine-grained measures when studying how we learn words

Word learning:When associative learning meets social-pragmatic expectations

How we learn words has been a long-standing debate in psycholinguistics. Social-pragmatic approaches argue that word learning is underpinned by learners’ social-cognitive abilities, which allow them to determine the communicative intentions of their interlocutors. Associative learning approaches, on the other hand, suggest that word learning is possible thanks to the human ability to track the frequency of co-occurrences between a word and its referent. An intermediate approach is the communicative/intentional framework, which posits that the relationship between a word and its referent is mediated by the speaker's intention to refer to a particular (set of) object(s). The studies presented in this dissertation take this assumption as their theoretical backdrop and pose two general research questions: 1) to what extent do social-pragmatic cues affect cross-situational word learning?; and 2) when in time do social-pragmatic effects emerge when learning words across situations? We designed five experiments that tested the effects of speaker reliability and speaker informativeness on cross-situational word learning. The results neither support nor contradict the hypothesis that exposure to an unreliable speaker results in learning fewer words and/or relying on associative learning mechanisms. Furthermore, the evidence that participants were sensitive to speaker reliability was inconsistent. However, when the effect of speaker informativeness on word learning was measured over time (by means of an eye-tracker), the results showed that speaker informativeness influenced the initial selection of objects as potential referents. This finding highlights the importance of fine-grained measures when studying how we learn words

Empowering a helper cluster through data-width aware instruction selection policies

Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor back-end features. Those attributes can be combined synergistically to design special clusters operating on narrow values (a.k.a. helper cluster), potentially providing performance benefits. We complement a 32-bit monolithic processor with a low-complexity 8-bit helper cluster. Then, in our main focus, we propose various ideas to select suitable instructions to execute in the data-width based clusters. We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load imbalance. Utilizing those techniques, the performance of a wide range of workloads are substantially increased; helper cluster achieves an average speedup of 11% for a wide range of 412 apps. When focusing on integer applications, the speedup can be as high as 22% on averagePeer ReviewedPostprint (published version

Near-optimal loop tiling by means of cache miss equations and genetic algorithms

The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a code transformation targeted to reduce capacity misses. This paper presents a novel systematic approach to perform near-optimal loop tiling based on an accurate data locality analysis (cache miss equations) and a powerful technique to search the solution space that is based on a genetic algorithm. The results show that this approach can remove practically all capacity misses for all considered benchmarks. The reduction of replacement misses results in a decrease of the miss ratio that can be as significant as a factor of 7 for the matrix multiply kernel.Peer ReviewedPostprint (published version

High-Performance low-vcc in-order core

Power density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. This paper presents a novel approach to decrease Vcc while keeping operating frequency high. Our mechanism is referred to as immediate read after write (IRAW) avoidance. We propose an implementation of the mechanism for an Intel® SilverthorneTM in-order core. Furthermore, we show that our mechanism can be adapted dynamically to provide the highest performance and lowest energy-delay product (EDP) at each Vcc level. Results show that IRAW avoidance increases operating frequency by 57% at 500mV and 99% at 400mV with negligible area and power overhead (below 1%), which translates into large speedups (48% at 500mV and 90% at 400mV) and EDP reductions (0.61 EDP at 500mV and 0.33 at 400mV).Peer ReviewedPostprint (published version

Fuse: A technique to anticipate failures due to degradation in ALUs

This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the adder appears, and hence, data corruption and program crashes can be avoided. Our results show that the fuse anticipates the failure in more than 99.9% of the cases after 96.6% of the lifetime, even for pessimistic random within-die variations.Peer ReviewedPostprint (published version