TINJAUAN HUKUM PEMBENTUKAN BADAN USAHA MILIK DESA (BUMDES) DITINJAU DARI UNDANG-UNDANG NOMOR 6 TAHUN 2014 TENTANG DESA

ABSTRACTLaw Number 6 of 2014 concerning Villages raises hope for the progress of the Village to increase its role in the economic system. Village-Owned Enterprises are regulated in CHAPTER X Article 87 paragraph 1 of Law Number 6 of 2014 concerning Villages, stating "Villages can establish Village-Owned Enterprises called BUMDes". In the Formation of Village-Owned Enterprises in Indonesia, there are still many villages that have not been able to form and do not understand how to establish Village-Owned Enterprises that have been mandated by the Village Law.The problem raised in this paper is how the process of forming a Village-Owned Enterprise is and what factors cause failure in the formation of a Village-Owned Enterprise. The type of research used is normative juridical research, based on researching library materials or secondary data consisting of primary legal materials, secondary legal materials and non-legal materials.The results showed that the process of forming a village-owned enterprise was carried out with the Village Deliberation to determine the name of the village-owned enterprise, select the board of directors, design and establish village regulations and articles of association, then register the village-owned enterprise at the ministry that carries out government affairs in the legal field. and human rights to obtain a legal entity certificate. Factors that cause failure in the formation of Village-Owned Enterprises are forming village-owned enterprises by trial and error without proper study, determining or choosing which business to run even though they do not master the chosen business, ending up giving up and being afraid to repeat, weak human resources and the limited basic infrastructure of a village

Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification

Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behavior of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a normalized histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate.Comment: 7 page

Live Demonstration: CNN Edge Computing for Mobile Robot Navigation

The brain cortex processes visual information to classify it following a scheme that has been mimicked by Convolutional Neural Networks (CNN). Specialised hardware accelerators are currently used as CPU co-processors for mobile applications. These accelerators are getting closer to the sensors for an edge computation of its output towards a faster and lower power consumption improvements. In this demonstration we use a dynamic vision sensor (inspired in the retina neural cells) as a visual source of the NullHop CNN accelerator deployed on a MPSoC FPGA and placed into a mobile robot for edge-computing the visual information and classify it to properly command a Summit-XL mobile robot for a target destiny. The reduced latency of the used CNN accelerator allows to process several histograms before taking a movement decision. A distance sensor mounted on the robot ensures that the direction change is done at the right distance for a proper path following

NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though Graphical Processing Units (GPUs) are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from 1x1 to 7x7. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq FPGA platform and present results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Post-synthesis simulations using Mentor Modelsim in a 28nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the MAC units, and achieves a power efficiency of over 3TOp/s/W in a core area of 6.3mm$^2$. As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real time interactive demonstrations

Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification

Deep-learning is a cutting edge theory that is being applied to many fields. For vision applications the Convolutional Neural Networks (CNN) are demanding significant accuracy for classification tasks. Numerous hardware accelerators have populated during the last years to improve CPU or GPU based solutions. This technology is commonly prototyped and tested over FPGAs before being considered for ASIC fabrication for mass production. The use of commercial typical cameras (30fps) limits the capabilities of these systems for high speed applications. The use of dynamic vision sensors (DVS) that emulate the behavior of a biological retina is taking an incremental importance to improve this applications due to its nature, where the information is represented by a continuous stream of spikes and the frames to be processed by the CNN are constructed collecting a fixed number of these spikes (called events). The faster an object is, the more events are produced by DVS, so the higher is the equivalent frame rate. Therefore, these DVS utilization allows to compute a frame at the maximum speed a CNN accelerator can offer. In this paper we present a VHDL/HLS description of a pipelined design for FPGA able to collect events from an Address-Event-Representation (AER) DVS retina to obtain a normalized histogram to be used by a particular CNN accelerator, called NullHop. VHDL is used to describe the circuit, and HLS for computation blocks, which are used to perform the normalization of a frame needed for the CNN. Results outperform previous implementations of frames collection and normalization using ARM processors running at 800MHz on a Zynq7100 in both latency and power consumption. A measured 67% speedup factor is presented for a Roshambo CNN real-time experiment running at 160fps peak rate

Conversaciones en pandemia

En este libro presentamos las transcripciones de las intervenciones realizadas en el ciclo de encuentros del CIM (Centro de Investigaciones en Mediatizaciones de la Universidad Nacional de Rosario, Argentina), realizado mediante la plataforma meet, y que denomináramos Conversaciones en PanMedia. Ante todo, nuestro agradecimiento a Mariana Ferrarelli, de cuyos trabajos académicos tomamos, en complicidad, la noción de “panmedia” aludiendo a esa mixtura y superposición de discursos, canales, actores, etc., que tan bien reseña Mariana en sus investigaciones. PanMedia nos permitía, así, un juego de desvíos de lo trágico a lo crítico-irónico -en sus múltiples formas-, de la aprehensión de y la aprensión a la PanDemia. Bajo esta simple demanda de entrar en conversación en épocas de aislamiento convocamos, entonces, a nuestros colegas del CIM e iniciamos, de tal modo, el diseño de una agenda de preocupaciones en común que va señalizando nuestra creciente inquietud.Fil: Valdettaro, Sandra. Universidad Nacional de Rosario. Facultad de Ciencia Política y Relaciones Internacionales; Argentina