Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives

Kierzynka M, Kosmann L, vor dem Berge M, et al. Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives. Future Generation Computer Systems. 2016;67:455-465

A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing

Kaiser M, Griessl R, Hagemeyer J, et al. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In: Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO; 2017

FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters

Griessl R, Peykanu M, Hagemeyer J, et al. FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters. Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA

A Low-Power Vision Processing Platform for Mobile Robots

Griessl R, Herbrechtsmeier S, Porrmann M, Rückert U. A Low-Power Vision Processing Platform for Mobile Robots. In: Proceedings of the FPL2011 Workshop on Computer Vision on Low-Power Reconfigurable Architectures. 2011.The paper proposes an implementation for a highly customizable FPGA-based vision processing module for mobile applications. The module can be ditrectly integrated into the AMiRo mini robot to anhance the robot’s vision processing capabilities while significantly reducing the CPU load. Dynamic reconfiguration can be utilized to further improve the resource utilization of the platform

FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers

Griessl R, Peykanu M, Tigges L, Hagemeyer J, Porrmann M. FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers. Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland

From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining

Lachmair J, Mieth T, Griessl R, Hagemeyer J, Porrmann M. From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining. In: International Joint Conference on Neural Networks (IJCNN 2017). 2017: 4299-4308

A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters

Griessl R, Peykanu M, Hagemeyer J, et al. A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. In: Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014. IEEE; 2014: 146-153

M2DC – A Novel Heterogeneous Hyperscale Microserver Platform

Oleksiak A, Kierzynka M, Porrmann M, et al. M2DC – A Novel Heterogeneous Hyperscale Microserver Platform. In: Kachris C, Falsafi B, Soudris D, eds. Hardware Accelerators in Data Centers. 1st ed. Cham, Switzerland: Springer International Publishing AG; 2019: 109-128

Data centres for IoT applications: The M2DC approach (Invited paper)

Oleksiak A, Porrmann M, Hagemeyer J, et al. Data centres for IoT applications: The M2DC approach (Invited paper). In: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). IEEE; 2016: 293-299.The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated; advanced management strategies and system efficiency enhancements (SEE); well-defined interfaces to surrounding software data centre ecosystem