On the design of efficient magnetic coils for the stimulation of peripheral nerves

pre-printNeural stimulators are the key building blocks of current neuroprosthetic systems, such as cochlear and retinal implants. Due to direct current injections and foreign body reactions, conventional current passing electrodes suffer from reduced performance and reduced lifetimes. However, magnetic fields can be used as an alternative technique to induce currents in neural tissues with the goal of stimulating the central and/or peripheral nervous systems (M. Yamaguchi et. al., JAP'89). Because the effectiveness of magnetic stimulation is directly related to the magnitude of the generated magnetic fields resulting from the current carried by a magnetic coil, the magnetic coil needs to be optimized to enhance the induced electric field at the stimulus site

Analysis of a Vendor Managed Consignment Inventory System with Kan-ban Withdrawals and Payment Delays

Vendor Managed Inventory (VMI) System with Consignment Inventory (CI) policy is a solution for many supply chain leaders in a highly competitive market. In this paper, totally eight different inventory supply chain models are studied. The profit function of supplier and manufacturer in different environments are compared in order to show the profitability of the overall supply chain management system in a manufacturing industry with different time horizons. The inventory systems are applied on a supply chain consisting of a single supplier and a manufacturer. The main focus of this study is to analyze the effect of payment deferral and the time value of money in push and pull (Kanban) manufacturing systems when VMI-CI policy is applied

SecDDR: Enabling Low-Cost Secure Memories by Protecting the DDR Interface

The security goals of cloud providers and users include memory confidentiality and integrity, which requires implementing Replay-Attack protection (RAP). RAP can be achieved using integrity trees or mutually authenticated channels. Integrity trees incur significant performance overheads and are impractical for protecting large memories. Mutually authenticated channels have been proposed only for packetized memory interfaces that address only a very small niche domain and require fundamental changes to memory system architecture. We propose SecDDR, a low-cost RAP that targets direct-attached memories, like DDRx. SecDDR avoids memory-side data authentication, and thus, only adds a small amount of logic to memory components and does not change the underlying DDR protocol, making it practical for widespread adoption. In contrast to prior mutual authentication proposals, which require trusting the entire memory module, SecDDR targets untrusted modules by placing its limited security logic on the DRAM die (or package) of the ECC chip. Our evaluation shows that SecDDR performs within 1% of an encryption-only memory without RAP and that SecDDR provides 18.8% and 7.8% average performance improvements (up to 190.4% and 24.8%) relative to a 64-ary integrity tree and an authenticated channel, respectively

Recent Advances in Neural Recording Microsystems

The accelerating pace of research in neuroscience has created a considerable demand for neural interfacing microsystems capable of monitoring the activity of large groups of neurons. These emerging tools have revealed a tremendous potential for the advancement of knowledge in brain research and for the development of useful clinical applications. They can extract the relevant control signals directly from the brain enabling individuals with severe disabilities to communicate their intentions to other devices, like computers or various prostheses. Such microsystems are self-contained devices composed of a neural probe attached with an integrated circuit for extracting neural signals from multiple channels, and transferring the data outside the body. The greatest challenge facing development of such emerging devices into viable clinical systems involves addressing their small form factor and low-power consumption constraints, while providing superior resolution. In this paper, we survey the recent progress in the design and the implementation of multi-channel neural recording Microsystems, with particular emphasis on the design of recording and telemetry electronics. An overview of the numerous neural signal modalities is given and the existing microsystem topologies are covered. We present energy-efficient sensory circuits to retrieve weak signals from neural probes and we compare them. We cover data management and smart power scheduling approaches, and we review advances in low-power telemetry. Finally, we conclude by summarizing the remaining challenges and by highlighting the emerging trends in the field

Aniruddh Ramrakhyani Thesis

The demise of Dennard Scaling and the continuance of Moore’s law has provided us with shrinking chip dimensions and higher on-chip transistor density at the cost of increas- ing power density. Chips today are highly power-constrained and often operate close to their melt-down energy thresholds. To avert the thermal meltdown of chip, designers use intelligent power-gating techniques. Here, the mode of operation is to power-up only a sub- set of IP blocks at a time. In addition to the power-density problem, decreasing transistor size has lead to decreasing silicon reliability which has led to increasing instances of on- chip faults. Both these effects lead to irregular on-chip topologies that change at runtime. Chip designers and architects today face the problem of routing packets over a dynamically changing irregular topology without sacrificing performance and more importantly without running into routing deadlocks. Another trend in the semi-conductor industry that has contibuted to the significance of this problem is the increasing use of heterogenous System-on-Chip (SoC). SoCs in most instances are tailored to the application needs. To maximise performance, these SoCs em- ploy custom-built irregular topologies to connect IP blocks. SoC designers have to to run a large number of simulations to understand the network traffic flows of the application it is being designed for. These simulation studies are carried out to ensure the absence of rout- ing deadlocks. This leads to increase in design time and consequently the time to market, leading to increase in costs and decrease in profits. Prior works in power-gating, resiliency and SoC design domains have addressed the routing deadlock problem by constructing a spanning-tree over the irregular topology and using it either as a deadlock avoidance mechanism (spanning-tree based routing) or as a deadlock-recovery mechanism (escape-vc) to route packets. However, this spanning-tree xi based solutions leads to significant loss in throughput and performance as shown in this work. In addition, a new spanning-tree construction is required every time the topology changes due to a fault in or power-gating of a network element. In this work, a new deadlock recovery framework called Static Bubble is proposed to achieve deadlock freedom in a static or dynamically changing irregular on-chip topology that doesn’t require any tree construction and thus is able to eliminate any overhead or limitations associated with the spanning-tree based solutions. Compared to the other state of the art works, static bubble provides upto 30% less latency, 4x more throughput and 50% less network EDP at less than 1% hardware overheadM.S