APENet: LQCD clusters a la APE

Developed by the APE group, APENet is a new high speed, low latency, 3-dimensional interconnect architecture optimized for PC clusters running LQCD-like numerical applications. The hardware implementation is based on a single PCI-X 133MHz network interface card hosting six indipendent bi-directional channels with a peak bandwidth of 676 MB/s each direction. We discuss preliminary benchmark results showing exciting performances similar or better than those found in high-end commercial network systems.Comment: Lattice2004(machines), 3 pages, 4 figure

An agent-based approach to assess drivers’ interaction with pre-trip information systems.

This article reports on the practical use of a multi-agent microsimulation framework to address the issue of assessing drivers’ responses to pretrip information systems. The population of drivers is represented as a community of autonomous agents, and travel demand results from the decision-making deliberation performed by each individual of the population as regards route and departure time. A simple simulation scenario was devised, where pretrip information was made available to users on an individual basis so that its effects at the aggregate level could be observed. The simulation results show that the overall performance of the system is very likely affected by exogenous information, and these results are ascribed to demand formation and network topology. The expressiveness offered by cognitive approaches based on predicate logics, such as the one used in this research, appears to be a promising approximation to fostering more complex behavior modelling, allowing us to represent many of the mental aspects involved in the deliberation process

High-speed data transfer with FPGAs and QSFP+ modules

We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ (Quad Small Form Pluggable +) module. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We implemented a complete testbench based on a commercial development card mounting an Altera Stratix IV FPGA with 24 serial transceivers at 8.5 Gbps, together with a custom mezzanine hosting three QSFP+ modules. We present test results and signal integrity measurements up to an aggregated bandwidth of 12 Gbps.Comment: 5 pages, 3 figures, Published on JINST Journal of Instrumentation proceedings of Topical Workshop on Electronics for Particle Physics 2010, 20-24 September 2010, Aachen, Germany(R Ammendola et al 2010 JINST 5 C12019

Correção do solo para cultivo do cajueiro no cerrado piauiense.

Caracteristicas dos solos cultivados com cajueiro no Piaui; Correcao do solo; Recomendacoesbitstream/CNPAT-2010/8606/1/Dc-081.pd

APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters

We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface technology plus hardware support for a RDMA programming model and experimental acceleration of GPU networking; this design allows us to build a low latency, high bandwidth PC cluster, the APEnet+ network, the new generation of our cost-effective, tens-of-thousands-scalable cluster network architecture. Some test results and characterization of data transmission of a complete testbench, based on a commercial development card mounting an Altera FPGA, are provided.Comment: 6 pages, 7 figures, proceeding of CHEP 2010, Taiwan, October 18-2

Etiological diagnosis, prognostic significance and role of electrophysiological study in patients with Brugada ECG and syncope.

BACKGROUND: Syncope is considered a risk factor for life-threatening arrhythmias in Brugada patients. Distinguishing a benign syncope from one due to ventricular arrhythmias is often difficult, unless an ECG is recorded during the episode. Aim of the study was to analyze the characteristics of syncopal episodes in a large population of Brugada patients and evaluate the role of electrophysiological study (EPS) and the prognosis in the different subgroups. METHODS AND RESULTS: One hundred ninety-five Brugada patients with history of syncope were considered. Syncope were classified as neurally mediated (group 1, 61%) or unexplained (group 2, 39%) on the basis of personal and family history, clinical features, triggers, situations, associated signs, concomitant therapy. Most patients underwent EPS; they received ICD or implantable loop-recorder on the basis of the result of investigations and physician's judgment. At 62±45months of mean follow-up, group 1 showed a significantly lower incidence of arrhythmic events (2%) as compared to group 2 (9%, p<0.001). Group 2 patients with positive EPS showed the highest risk of arrhythmic events (27%). No ventricular events occurred in subjects with negative EPS. CONCLUSION: Etiological definition of syncope in Brugada patients is important, as it allows identifying two groups with different outcome. Patients with unexplained syncope and ventricular fibrillation induced at EPS have the highest risk of arrhythmic events. Patients presenting with neurally mediated syncope showed a prognosis similar to that of the asymptomatic and the role of EPS in this group is unproven

NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features

While the GPGPU paradigm is widely recognized as an effective approach to high performance computing, its adoption in low-latency, real-time systems is still in its early stages. Although GPUs typically show deterministic behaviour in terms of latency in executing computational kernels as soon as data is available in their internal memories, assessment of real-time features of a standard GPGPU system needs careful characterization of all subsystems along data stream path. The networking subsystem results in being the most critical one in terms of absolute value and fluctuations of its response latency. Our envisioned solution to this issue is NaNet, a FPGA-based PCIe Network Interface Card (NIC) design featuring a configurable and extensible set of network channels with direct access through GPUDirect to NVIDIA Fermi/Kepler GPU memories. NaNet design currently supports both standard - GbE (1000BASE-T) and 10GbE (10Base-R) - and custom - 34~Gbps APElink and 2.5~Gbps deterministic latency KM3link - channels, but its modularity allows for a straightforward inclusion of other link technologies. To avoid host OS intervention on data stream and remove a possible source of jitter, the design includes a network/transport layer offload module with cycle-accurate, upper-bound latency, supporting UDP, KM3link Time Division Multiplexing and APElink protocols. After NaNet architecture description and its latency/bandwidth characterization for all supported links, two real world use cases will be presented: the GPU-based low level trigger for the RICH detector in the NA62 experiment at CERN and the on-/off-shore data link for KM3 underwater neutrino telescope

Período apropriado para a substituição de copa do cajueiro anão precoce ou para a enxertia direta no campo.

O estudo tem o objetivo de apresentar uma alternativa para formacão de pomares de cajueiro anão precoce, em razão da grande dificuldade de disponibilidade de mudas enxertadas a época própria para plantio.bitstream/CNPAT-2010/11938/1/Pa-044.pd

Custo comparativo de três fontes de matéria orgânica e uma poliacrilamida utilizadas como condicionadores de solo na produção do meloeiro.

Custo comparativo de três fontes de matéria orgânica e uma poliacrilamida utilizadas como condicionadores de solo na produção do meloeiro.bitstream/CNPAT-2010/5297/1/Ct-015.pd