Reliability approach of high density Through Silicon Via (TSV)

ISBN 978-1-4244-8561-1International audienceThis paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV), and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (EM) tests. Physical analyses reveal the presence of a carbon impurity layer at bottom of the higher resistance TSVs. This impurity induces failure during TCT, but has no impact on EM time to failure distribution. We also discuss the relevance of different electrical resistance failure criterions after TCT for a single TSV

Resistance Increase Due to Electromigration Induced Depletion Under TSV

ISBN 978-1-4244-9111-7International audience3D-IC integration using Through Silicon Via (TSV) is becoming an alternative to overcome obstacles of CMOS scaling. As TSV processes reach maturity, reliability investigation becomes critical. To the best of our knowledge, we propose for the first time an analytical model of resistance increase due to electromigration induced voiding in a line ended by a TSV

Solid phase epitaxy process integration on 50-nm PMOS devices: Effects of defects on chemical and electrical characteristics of ultra shallow junctions

International audienceWe demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2 for Source/Drain, reduces the junction leakage by two decades

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

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« Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs”

International audienc

Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

International audienc

« Investigation on TSV impact on 65nm CMOS devices and circuits »

International audienc

Investigation on TSV impact on 65nm CMOS devices and circuits

International audienc

Investigation on TSV impact on 65nm CMOS devices and circuits

International audienc