ANÁLISE DO VOLTAGE SCALING EM PORTAS LÓGICAS XOR UTILIZANDO DISPOSITIVOS FINFET

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Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity

International audienceThe design methodology based on standard cells is widely used in a broad range of VLSI applications. Further, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This work evaluates the implications of the usage of complex-logic cells from a 45 nm Standard-Cell library to the Single-Event Transient sensitivity under heavy ions. Results show that even though a reduction in the layout area is obtained when adopting complex-logic gates, a slight reduction in the total sensitive area of the circuit is observed. Moreover, the effectiveness of logical masking can be suppressed, leading to a higher SET cross-section

Outil de prédictions et durcissement par design pour les SET et SEU

The reliability of electronic circuits is subject to physical damage or functional failures due to the influence of the application environment, such as the presence of atmospheric or space radiation. The particle interaction within silicon can lead to permanent or transient effects such as the Single-Event Effects (SEEs). Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET must be carefully addressed along with the SEU characterization in electronics systems from space to ground applications. Also, to increase the reliability of the systems, radiation hardening techniques can be adopted in the process or design levels. The characterization process is usually experimental-test oriented, however, the need of adopting modeling simulations to study fundamental radiation effects and improve testing methodologies has led to an increase interest in developing SEE characterization methodologies based on simulation tools. Accordingly, this thesis provides a complete simulation chain based on a multi-physics and multi-scale approach to characterize electronics component against SEU/SET effects. Additionally, radiation-hardening-by-design (RHBD) techniques were evaluated and proposed at physical layout and circuit levels. The physical layout design influences the SEE generation mechanisms induced by a particle strike hence hardening techniques are widely used in the layout level to reduce the charge collection process. Besides analyzing the gate sizing and transistor stacking, in this work, the transistor folding layout is proposed along with the diffusion splitting technique. The results have shown that folded designs can provide lower SET cross-section in addition to the higher threshold LET than the observed for the unfolded designs. At circuit-level, the implications of logic synthesis of cell-based designs are studied. Additionally, given the input dependence of the RHBD techniques, signal probability is proposed as an application-specific hardening approach in order to improve the hardening efficiency while reducing the design drawbacks and, very importantly, avoid misleading qualifications. For instance, a pin assignment optimization targeting SET effects can provide reduction on the overall SET rate without any area overhead. Additionally, selective TMR (Triple Modular Redundancy) block insertion methodologies can be optimized based on the signal probability of the critical nodes and the majority voter architectures.La fiabilité des circuits électroniques est sujette à des dommages physiques ou à des défaillances fonctionnelles en raison de la présence du rayonnement atmosphérique ou spatial. L'interaction des particules dans le silicium peut entraîner des effets permanents ou transitoires tels que les effets d’événement singulier (SEE). En raison des effets de masquage intrinsèques des circuits combinatoires dans les conceptions numériques, les événements singuliers transitoires (SET) ont été considérés comme non pertinents par rapport à la rupture de données causée par les aléas logiques (SEU). Cependant, l'importance de considérer les SETs dans les circuits VLSI (Very-Large-System-Integration) augmente étant donnée la réduction des dimensions des transistors et de la profondeur du chemin de données logique dans les technologies avancées. En conséquence, la menace associée aux SET doit être soigneusement traitée en même temps que la caractérisation du SEU dans les systèmes électroniques des applications spatiales, avioniques et même pour les applications au sol. De plus, pour augmenter la fiabilité des systèmes, des techniques de durcissement peuvent être adoptées dans les niveaux de processus ou de conception. Le processus de caractérisation est généralement orienté vers les tests expérimentaux, mais la nécessité d'adopter des simulations de modélisation pour étudier les effets fondamentaux des rayonnements et améliorer les méthodologies de test a conduit à un intérêt accru pour le développement de méthodologies de caractérisation des SEEs basées sur des outils de simulation. En conséquence, cette thèse fournit une chaîne de simulation numérique complète basée sur une approche multi-physique et multi-échelle pour caractériser les composants électroniques contre les effets SEU / SET. De plus, des techniques de durcissement par design (RHBD) ont été évaluées et proposées au niveau du layout physique et du circuit. La conception du layout physique influence les mécanismes de génération de SEE induits par une collision des particules. Par conséquent, les techniques de durcissement sont largement utilisées au niveau du layout pour réduire le processus de collecte des charges. Au-delà de l'analyse du dimensionnement et de l’empilage des transistors, ce travail propose l’utilisation du layout de transistors repliés ainsi que la technique de « diffusion splitting ». Les résultats ont indiqué que les designs repliés peuvent offrir une section efficace de SET inférieure ainsi qu'un LET seuil plus élevé que celui observé pour les designs non repliés. Au niveau des circuits, les implications de la synthèse logique des conceptions à base de cellules sont étudiées. En outre, étant donné la dépendance des techniques RHBD par rapport au signal d'entrée, la probabilité du signal est proposée comme une approche de durcissement spécifique à l'application afin d'améliorer l'efficacité du durcissement tout en réduisant les inconvénients de conception et d'éviter les qualifications trompeuses. Par exemple, une optimisation de l'affectation des broches qui vise les effets SET peut permettre de réduire le taux global de SET. De plus, les méthodologies d'insertion sélective de blocs TMR (Triple Modular Redundancy) peuvent être optimisées en fonction de la probabilité de signal des nœuds critiques et des architectures de votes majoritaires

Radiation robustness of XOR and majority voter circuits at finFET technology under variability

Advances in microelectronics have contributed to the size reduction of the technological node, lowering the threshold voltage and increasing the operating frequency of the systems. Although it has positive outcomes related to the performance and power consumption of VLSI circuits, it does also have a strong negative impact in terms of the reliability of designs. As technology scales down, the circuits are becoming more susceptible to numerous effects due to the reduction of robustness to external noise as well as the increase of uncertainty degree related to the many sources of variability. Faulttolerant techniques are usually used to improve the robustness of safety critical applications. However, the implications of the scaling of technology have interfered against the effectiveness of fault-tolerant approaches to provide the fault coverage. For this reason, this work has evaluated the radiation robustness of different circuits designed in FinFET technology under variability effects. In order to determine the best design options to implement fault-tolerant techniques such as the Triple-Module Redundancy (TMR) and/or Duplication with Comparison (DWC) schemes, the set of analyzed circuits is composed of ten different exclusive-OR (XOR) logic gate topologies and two majority voter (MJV) circuits. To investigate the effect of gate configuration of FinFET devices, the XOR circuits is analyzed using double-gate configuration (DG FinFET) and tri-gate configuration (TG FinFET). Environmental Variability such as Temperature and Voltage Variability are evaluated in the set of analyzed circuits. Additionally, the process-related variability effect Work-Function Fluctuation (WFF) is also evaluated. In order to provide a more precise study, the layout design of the MJV circuits using a 7nm FinFET PDK is evaluated by the predictive MUSCA SEP3 tool to estimate the Soft-Error Rate (SER) of the circuits considering the layout contrainsts and Back-End-Of-Line (BEOL) and Front-End-Of-Line (FEOL) layers of an advanced technology node.Os avanços na microeletrônica contribuíram para a redução de tamanho do nó tecnológico, diminuindo a tensão de limiar e aumentando a freqüência de operação dos sistemas. Embora tenha resultado em ganhos positivos relacionados ao desempenho e ao consumo de energia dos circuitos VLSI, a miniaturização também tem um impacto negativo em termos de confiabilidade dos projetos. À medida que a tecnologia diminui, os circuitos estão se tornando mais suscetíveis a inúmeros efeitos devido à redução da robustez ao ruído externo, bem como ao aumento do grau de incerteza relacionado às muitas fontes de variabilidade. As técnicas de tolerancia a falhas geralmente são usadas para melhorar a robustez das aplicações de segurança crítica. No entanto, as implicações da redução da tecnologia interferem na eficácia de tais abordagem em fornecer a cobertura de falhas desejada. Por esse motivo, este trabalho avaliou a robustez aos efeitos de radiação de diferentes circuitos projetados na tecnologia FinFET sob efeitos de variabilidade. Para determinar as melhores opções de projeto para implementar técnicas de tolerancia a falhas, como os esquemas de Redundância de módulo triplo (TMR) e/ou duplicação com comparação (DWC), o conjunto de circuitos analisados é composto por dez diferentes topologias de porta lógica OR-exclusivo (XOR) e dois circuitos votadores maioritários (MJV). Para investigar o efeito da configuração do gate dos dispositivos FinFET, os circuitos XOR são analisados usando a configuração de double-gate (DG FinFET) e tri-gate (TG FinFET). A variabilidade ambiental, como variabilidade de temperatura e tensão, são avaliadas no conjunto de circuitos analisados. Além disso, o efeito da variabilidade de processo Work-Function Fluctuation (WFF) também é avaliado. A fim de fornecer um estudo mais preciso, o projeto do leiaute dos circuitos MJV usando 7nm FinFET PDK é avaliado pela ferramenta preditiva MUSCA SEP3 para estimar o Soft-Error Rate (SER) dos circuitos considerando as características do leiaute e as camadas de Back-End-Of-Line (BEOL) e Front-End-Of-Line (FEOL) de um nó tecnológico avançado

Radiation robustness of XOR and majority voter circuits at finFET technology under variability

Advances in microelectronics have contributed to the size reduction of the technological node, lowering the threshold voltage and increasing the operating frequency of the systems. Although it has positive outcomes related to the performance and power consumption of VLSI circuits, it does also have a strong negative impact in terms of the reliability of designs. As technology scales down, the circuits are becoming more susceptible to numerous effects due to the reduction of robustness to external noise as well as the increase of uncertainty degree related to the many sources of variability. Faulttolerant techniques are usually used to improve the robustness of safety critical applications. However, the implications of the scaling of technology have interfered against the effectiveness of fault-tolerant approaches to provide the fault coverage. For this reason, this work has evaluated the radiation robustness of different circuits designed in FinFET technology under variability effects. In order to determine the best design options to implement fault-tolerant techniques such as the Triple-Module Redundancy (TMR) and/or Duplication with Comparison (DWC) schemes, the set of analyzed circuits is composed of ten different exclusive-OR (XOR) logic gate topologies and two majority voter (MJV) circuits. To investigate the effect of gate configuration of FinFET devices, the XOR circuits is analyzed using double-gate configuration (DG FinFET) and tri-gate configuration (TG FinFET). Environmental Variability such as Temperature and Voltage Variability are evaluated in the set of analyzed circuits. Additionally, the process-related variability effect Work-Function Fluctuation (WFF) is also evaluated. In order to provide a more precise study, the layout design of the MJV circuits using a 7nm FinFET PDK is evaluated by the predictive MUSCA SEP3 tool to estimate the Soft-Error Rate (SER) of the circuits considering the layout contrainsts and Back-End-Of-Line (BEOL) and Front-End-Of-Line (FEOL) layers of an advanced technology node.Os avanços na microeletrônica contribuíram para a redução de tamanho do nó tecnológico, diminuindo a tensão de limiar e aumentando a freqüência de operação dos sistemas. Embora tenha resultado em ganhos positivos relacionados ao desempenho e ao consumo de energia dos circuitos VLSI, a miniaturização também tem um impacto negativo em termos de confiabilidade dos projetos. À medida que a tecnologia diminui, os circuitos estão se tornando mais suscetíveis a inúmeros efeitos devido à redução da robustez ao ruído externo, bem como ao aumento do grau de incerteza relacionado às muitas fontes de variabilidade. As técnicas de tolerancia a falhas geralmente são usadas para melhorar a robustez das aplicações de segurança crítica. No entanto, as implicações da redução da tecnologia interferem na eficácia de tais abordagem em fornecer a cobertura de falhas desejada. Por esse motivo, este trabalho avaliou a robustez aos efeitos de radiação de diferentes circuitos projetados na tecnologia FinFET sob efeitos de variabilidade. Para determinar as melhores opções de projeto para implementar técnicas de tolerancia a falhas, como os esquemas de Redundância de módulo triplo (TMR) e/ou duplicação com comparação (DWC), o conjunto de circuitos analisados é composto por dez diferentes topologias de porta lógica OR-exclusivo (XOR) e dois circuitos votadores maioritários (MJV). Para investigar o efeito da configuração do gate dos dispositivos FinFET, os circuitos XOR são analisados usando a configuração de double-gate (DG FinFET) e tri-gate (TG FinFET). A variabilidade ambiental, como variabilidade de temperatura e tensão, são avaliadas no conjunto de circuitos analisados. Além disso, o efeito da variabilidade de processo Work-Function Fluctuation (WFF) também é avaliado. A fim de fornecer um estudo mais preciso, o projeto do leiaute dos circuitos MJV usando 7nm FinFET PDK é avaliado pela ferramenta preditiva MUSCA SEP3 para estimar o Soft-Error Rate (SER) dos circuitos considerando as características do leiaute e as camadas de Back-End-Of-Line (BEOL) e Front-End-Of-Line (FEOL) de um nó tecnológico avançado

ANÁLISE DO VOLTAGE SCALING EM PORTAS LÓGICAS XOR UTILIZANDO DISPOSITIVOS FINFET

1

Analysis of the charge sharing effect in the SET sensitivity of bulk 45nm standard cell layouts under heavy ions

International audienc

Analysis of the charge sharing effect in the SET sensitivity of bulk 45nm standard cell layouts under heavy ions

International audienc

Impact of Complex-Logic Cell Layout on the Single-Event Transient Sensitivity

International audienceThe design methodology based on standard cells is widely used in a broad range of VLSI applications. Further, several optimization algorithms can be employed to address different constraints such as power consumption or reliability. This work evaluates the implications of the usage of complex-logic cells from a 45 nm Standard-Cell library to the Single-Event Transient sensitivity under heavy ions. Results show that even though a reduction in the layout area is obtained when adopting complex-logic gates, a slight reduction in the total sensitive area of the circuit is observed. Moreover, the effectiveness of logical masking can be suppressed, leading to a higher SET cross-section

Effect of Temperature on Single Event Latchup Sensitivity

International audienceSingle-Event Latchup (SEL) concerns CMOS technology as a major reliability issue and it is influenced by different parameters. In this work, the effect of the temperature variation on SELhas been investigated and its effect has been analyzed combining the variation of three parameters related to the geometry and to the design of the component: doping profile, anode to cathode spacing (A-C spacing) and substrate and well taps placement. 2D TCAD simulations have been performed, using an NPNP structure based on 65nm CMOS inverter. From these simulations, we have analyzed threshold LET and SEL rate. Results show that temperature impact is stronger when the component is less sensitive to SEL