153 research outputs found

    Improvements in Hardware Transactional Memory for GPU Architectures

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    In the multi-core CPU world, transactional memory (TM)has emerged as an alternative to lock-based programming for thread synchronization. Recent research proposes the use of TM in GPU architectures, where a high number of computing threads, organized in SIMT fashion, requires an effective synchronization method. In contrast to CPUs, GPUs offer two memory spaces: global memory and local memory. The local memory space serves as a shared scratch-pad for a subset of the computing threads, and it is used by programmers to speed-up their applications thanks to its low latency. Prior work from the authors proposed a lightweight hardware TM (HTM) support based in the local memory, modifying the SIMT execution model and adding a conflict detection mechanism. An efficient implementation of these features is key in order to provide an effective synchronization mechanism at the local memory level. After a quick description of the main features of our HTM design for GPU local memory, in this work we gather together a number of proposals designed with the aim of improving those mechanisms with high impact on performance. Firstly, the SIMT execution model is modified to increase the parallelism of the application when transactions must be serialized in order to make forward progress. Secondly, the conflict detection mechanism is optimized depending on application characteristics, such us the read/write sets, the probability of conflict between transactions and the existence of read-only transactions. As these features can be present in hardware simultaneously, it is a task of the compiler and runtime to determine which ones are more important for a given application. This work includes a discussion on the analysis to be done in order to choose the best configuration solution.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

    Towards a Software Transactional Memory for heterogeneous CPU-GPU processors

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    The heterogeneous Accelerated Processing Units (APUs) integrate a multi-core CPU and a GPU within the same chip. Modern APUs provide the programmer with platform atomics, used to communicate the CPU cores with the GPU using simple atomic datatypes. However, ensuring consistency for complex data types is a task delegated to programmers, who have to implement a mutual exclusion mechanism. Transactional Memory (TM) is an optimistic approach to implement mutual exclusion. With TM, shared data can be accessed by multiple computing threads speculatively, but changes are only visible if a transaction ends with no conflict with others in its memory accesses. TM has been studied and implemented in software and hardware for both CPU and GPU platforms, but an integrated solution has not been provided for APU processors. In this paper we present APUTM, a software TM designed to work on heterogeneous APU processors. The design of APUTM focuses on minimizing the access to shared metadata in order to reduce the communication overhead via expensive platform atomics. The main objective of APUTM is to help us understand the tradeoffs of implementing a sofware TM on an heterogeneous CPU-GPU platform and to identify the key aspects to be considered in each device. In our experiments, we compare the adaptability of APUTM to execute in one of the devices (CPU or GPU) or in both of them simultaneously. These experiments show that APUTM is able to outperform sequential execution of the applications.This work has been supported by projects TIN2013-42253-P and TIN2016-80920-R, from the Spanish Government, P11-TIC8144 and P12- TIC1470, from Junta de Andalucía, and Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

    Reflexiones acerca de la vida de cada día en la Ucrania post-sovietica

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    El autor, después de pasar un año en Ucrania, como profesor visitante, reflexiona acerca de la realidad social, política y económica en ese país. A pesar de estar consciente de que hoy se habla de postmodernismo, considera a Ucrania como una sociedad- industrial, pero no moderna, ya que carece de los procedimientos, valores y comodidades de la modernidad. Constata, además, el fracaso absoluto del modelo de industrialización comunista. Finalmente, estima que la política doméstica, con un necesario y reforzado Estado de Derecho, y sus relaciones internacionales, especialmente las vecinales, definirán el futuro de Ucrania

    Hardware support for Local Memory Transactions on GPU Architectures

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    Graphics Processing Units (GPUs) are popular hardware accelerators for data-parallel applications, enabling the execution of thousands of threads in a Single Instruction - Multiple Thread (SIMT) fashion. However, the SIMT execution model is not efficient when code includes critical sections to protect the access to data shared by the running threads. In addition, GPUs offer two shared spaces to the threads, local memory and global memory. Typical solutions to thread synchronization include the use of atomics to implement locks, the serialization of the execution of the critical section, or delegating the execution of the critical section to the host CPU, leading to suboptimal performance. In the multi-core CPU world, transactional memory (TM) was proposed as an alternative to locks to coordinate concurrent threads. Some solutions for GPUs started to appear in the literature. In contrast to these earlier proposals, our approach is to design hardware support for TM in two levels. The first level is a fast and lightweight solution for coordinating threads that share the local memory, while the second level coordinates threads through the global memory. In this paper we present GPU-LocalTM as a hardware TM (HTM) support for the first level. GPU-LocalTM offers simple conflict detection and version management mechanisms that minimize the hardware resources required for its implementation. For the workloads studied, GPU-LocalTM provides between 1.25-80X speedup over serialized critical sections, while the overhead introduced by transaction management is lower than 20%.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

    Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

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    Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.Universidad de Málaga. Campus de Excelencia Internacional Andalucía Tech

    La verdad y el trato crativo en el cine documental

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    Treballs de l'alumnat del Grau de Comunicació Audiovisual, Facultat de Biblioteconomia i Documentació, Universitat de Barcelona, Treball Final de Grau - TFG. Curs: 2013-2014, Tutores: Paula Ortiz Álvarez i Lydia Sánchez GómezEste Trabajo de Fin de Grado de la carrera de Comunicación Audiovisual de la Universidad de Barcelona trata de una investigación teórico-práctica sobre el campo de la ética en el cine documental. Se plantean cuestiones relacionadas con la utilización de recursos audiovisuales más típicamente utilizados en ficción, tales como recreación y reconstrucción de escenas en platós, utilización de actores, uso de la animación por ordenador, u otros tipos de implicación creativa por parte del realizador y de su equipo técnico. A partir de esto se plantea una reflexión sobre su uso lícito y ético, teniendo en cuenta que la utilización de estos recursos merma la objetividad de los hechos narrados en el documental. Además, se ha escrito un guion literario de falso documental en el que aplicar las distintas convenciones propias del género a la vez que plantear, en una selección de escenas, la posible aplicación de estos recursos creativos, desde un punto de vista de logística y producción audiovisual

    Desarrollo de una metodología que permita determinar en forma previa la condición AR.I.MA. de una o múltiples series de tiempo, en un programa de base Excel, para predicciones e inventarios en mantenimiento

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    La metodología de series de tiempo, analiza las características de los datos del presente y del pasado, para proyectarlas hacia el futuro, donde se infiere que las causas que originan el comportamiento en el pasado y en el presente, son los mismos que condicionan el comportamiento futuro (Makridakis, y otros, 1978). La metodología de series temporales ofrece unos niveles de precisión entre lo predicho y la realidad cercanos e inferiores al 11%. Su metodología se basa en los principios de desarrollo del método científico: observación y análisis, hipótesis y verificación (Carrión, 1999).61 p.Contenido parcial: Series de tiempo -- Criterios estadísticos en series de tiempo -- Cumplimiento de criterios estadísticos -- Uso de aplicación en base Excel -- Medida del grado de acierto en las predicciones

    Criterios de subcontratación en mantenimiento textil en el Valle de Aburrá

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