20 research outputs found

    Instytut Technologii Materiałów Elektronicznych w ocenie międzynarodowej

    No full text
    Oceną poziomu naukowego, innowacyjności i konkurencyjności państw, przedsiębiorstw i instytucji naukowych zajmuje się wiele organizacji. Do najbardziej znanych rankingów przedstawiających ocenę innowacyjności poszczególnych państw należy Global Innovation Index [1], a oceny konkurencyjności państw, których jednym z elementów jest innowacyjność podaje Global Competitiveness Report [2], przedstawiany corocznie na Światowym Forum Ekonomicznym

    Magnetostratigraphy of the Campanian/Maastrichtian boundary succession from the Middle Vistula River section, Central Poland

    No full text
    The magnetic polarities of the upper Upper Campanian–Lower Maastrichtian interval of the Middle Vistula River composite section (central Poland), were studied. Sixty-six hand-oriented samples for palaeomagnetic studies were taken from the sections of Raj, Raj North, Podole, Kłudzie and Dziurków. The inter-correlation between them is based primarily on bio-events. The sampled rocks generally revealed a very weak magnetic signal, however quite reliable results were obtained. The whole interval studied, well constrained biostratigraphically, is referred to magnetostratigraphic chron C32n. The Campanian–Maastrichtian boundary, placed biostratigraphically in the upper part of the ‘Inoceramus’ redbirdensis inoceramid Zone, is located near the top of the C32n2n Subchron. Thin reversed polarity intervals in the rocks correlated with the C32n2n chron most probably result from their partial remagnetization (maghemitization)

    The Institute of Electronic Materials Technology in SCIMAGO Ranking in years 2014-2020

    No full text
    One of the most prestigious worldwide rankings of scientific institution is the Global SCIMAGO Institutions Rankings (SIR) [1]. The results are annually published by SCIMAGO Lab [2] and are based on SCOPUS publication database. The SIR rankings in a given year cover all scientific institutions that have published more than 100 publications the year before. The evaluated institutions are grouped by sectors: Universities, Health, Government, Companies and Non-Profit

    Experimental population dynamics of Rhabdias bufonis

    No full text

    NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

    No full text
    A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program
    corecore