151 research outputs found
Copernicus high-resolution layers for land cover classification in Italy
The high-resolution layers (HRLs) are land cover maps produced for the entire Italian territory (approximately 30 million hectares) in 2012 by the European Environment Agency, aimed at monitoring soil imperviousness and natural cover, such as forest, grassland, wetland, and water surface, with a high spatial resolution of 20 m. This study presents the methodologies developed for the production, verification, and enhancement of the HRLs in Italy. The innovative approach is mainly based on (a) the use of available reference data for the enhancement process, (b) the reduction of the manual work of operators by using a semi-automatic approach, and (c) the overall increase in the cost-efficiency in relation to the production and updating of land cover maps. The results show the reliability of these methodologies in assessing and enhancing the quality of the HRLs. Finally, an integration of the individual layers, represented by the HRLs, was performed in order to produce a National High-Resolution Land Cover ma
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers
Processors using the open RISC-V ISA are finding increasing adoption in the
embedded world. Many embedded use cases have real-time constraints and require
flexible, predictable, and fast reactive handling of incoming events. However,
RISC- V processors are still lagging in this area compared to more mature
proprietary architectures, such as ARM Cortex-M and TriCore, which have been
tuned for years. The default interrupt controller standardized by RISC-V, the
Core Local Interruptor (CLINT), lacks configurability in prioritization and
preemption of interrupts. The RISC-V Core Local Interrupt Controller (CLIC)
specification addresses this concern by enabling pre-emptible, low-latency
vectored interrupts while also envisioning optional extensions to improve
interrupt latency. In this work, we implement a CLIC for the CV32E40P, an
industrially supported open-source 32-bit MCU-class RISC-V core, and enhance it
with fastirq: a custom extension that provides interrupt latency as low as 6
cycles. We call CV32RT our enhanced core. To the best of our knowledge, CV32RT
is the first fully open-source RV32 core with competitive interrupt-handling
features compared to the Arm Cortex-M series and TriCore. The proposed
extensions are also demonstrated to improve task context switching in real-time
operating systems.Comment: 12 pages, submitted to IEEE Transactions on VLSI Systems (TVLSI
To Know or Not To Know: Strategic Inattention and Endogenous Market Structure
We model an industry in which a discrete number of firms choose the output of their differentiated products deciding whether or not to consider the impact of their decisions on aggregate output. We show that two threshold numbers of firms exist such that: below the lower one there is a unique equilibrium in which all firms consider their aggregate impact as in standard oligopoly; above the higher threshold
there is a unique equilibrium in which all firms disregard that impact as in standard monopolistic competition; between the two thresholds there are two equilibria, one in which all firms consider their aggregate impact and the other in which they do not. We then show that our
model of strategic inattention is isomorphic to a model of strategic delegation with managerial compensation based on relative profit performance
Dream jobs
Understanding why certain jobs are ‘better’ than others and what implications they have for a worker’s career is clearly an important but still relatively unexplored question. We provide both a theoretical framework and a number of empirical results that help distinguishing ‘good’ from ‘bad’ jobs in terms of their impact on a worker’s lifetime wage income profile through wage jumps occurring upon changing job (‘static effects’) or through increases in the wage growth rate (‘dynamic effects’). We find that the distinction between internationally active firms and domestic firms is a meaningful empirical dividing line between employers providing ‘good’ and ‘bad’ jobs. First, in internationally active firms the experience-wage profile is much steeper than in domestic firms, especially for managers as opposed to blue-collar workers. Second, the higher lifetime wage income for managers in internationally active firms relies on the stronger accumulation of experience that these firms allow for and on the (almost) perfect portability of the accumulated dynamic wage gains to other firms. Static effects are instead much more important for blue-collar workers. Finally, the distinction between internationally active and domestic firms is relevant also at a more aggregate level to explain cross-sectional differences in wages among workers and spatial differences in average wages across regions within a country.info:eu-repo/semantics/publishedVersio
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
Extensive polling in shared-memory manycore systems can lead to contention,
decreased throughput, and poor energy efficiency. Both lock implementations and
the general-purpose atomic operation, load-reserved/store-conditional (LRSC),
cause polling due to serialization and retries. To alleviate this overhead, we
propose LRwait and SCwait, a synchronization pair that eliminates polling by
allowing contending cores to sleep while waiting for previous cores to finish
their atomic access. As a scalable implementation of LRwait, we present
Colibri, a distributed and scalable approach to managing LRwait reservations.
Through extensive benchmarking on an open-source RISC-V platform with 256
cores, we demonstrate that Colibri outperforms current synchronization
approaches for various concurrent algorithms with high and low contention
regarding throughput, fairness, and energy efficiency. With an area overhead of
only 6%, Colibri outperforms LRSC-based implementations by a factor of 6.5x in
terms of throughput and 7.1x in terms of energy efficiency.Comment: 6 pages, 6 figures, 2 tables, accepted as a regular paper at DATE2
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors
A key challenge for ultra-low-power (ULP) devices is handling peripheral
linking, where the main central processing unit (CPU) periodically mediates the
interaction among multiple peripherals following wake-up events. Current
solutions address this problem by either integrating event interconnects that
route single-wire event lines among peripherals or by general-purpose I/O
processors, with a strong trade-off between the latency, efficiency of the
former, and the flexibility of the latter. In this paper, we present an
open-source, peripheral-agnostic, lightweight, and flexible Peripheral Event
Linking System (PELS) that combines dedicated event routing with a tiny I/O
processor. With the proposed approach, the power consumption of a linking event
is reduced by 2.5 times compared to a baseline relying on the main core for the
event-linking process, at a low area of just 7 kGE in its minimal
configuration, when integrated into a ULP RISC-V IoT processor.Comment: 6 pages, accepted at DATE24 conference, camera-ready versio
Towards a RISC-V Open Platform for Next-generation Automotive ECUs
The complexity of automotive systems is increasing quickly due to the
integration of novel functionalities such as assisted or autonomous driving.
However, increasing complexity poses considerable challenges to the automotive
supply chain since the continuous addition of new hardware and network cabling
is not considered tenable. The availability of modern heterogeneous
multi-processor chips represents a unique opportunity to reduce vehicle costs
by integrating multiple functionalities into fewer Electronic Control Units
(ECUs). In addition, the recent improvements in open-hardware technology allow
to further reduce costs by avoiding lock-in solutions.
This paper presents a mixed-criticality multi-OS architecture for automotive
ECUs based on open hardware and open-source technologies. Safety-critical
functionalities are executed by an AUTOSAR OS running on a RISC-V processor,
while the Linux OS executes more advanced functionalities on a multi-core ARM
CPU. Besides presenting the implemented stack and the communication
infrastructure, this paper provides a quantitative gap analysis between an
HW/SW optimized version of the RISC-V processor and a COTS Arm Cortex-R in
terms of real-time features, confirming that RISC-V is a valuable candidate for
running AUTOSAR Classic stacks of next-generation automotive MCUs.Comment: 8 pages, 2023 12th Mediterranean Conference on Embedded Computing
(MECO
Well-being Forecasting using a Parametric Transfer-Learning method based on the Fisher Divergence and Hamiltonian Monte Carlo
INTRODUCTION: Traditional personalised modelling typically requires sufficient personal data for training. This is a challenge in healthcare contexts, e.g. when using smartphones to predict well-being.
OBJECTIVE: A method to produce incremental patient-specific models and forecasts even in the early stages of data collection when the data are sporadic and limited.
METHODS: We propose a parametric transfer-learning method based on the Fisher divergence, where information from other patients is injected as a prior term into a Hamiltonian Monte Carlo framework. We test our method on the NEVERMIND dataset of self-reported well-being scores.
RESULTS: Out of 54 scenarios representing varying training/forecasting lengths and competing methods, our method achieved overall best performance in 50 (92.6%) and demonstrated a significant median difference in45 (83.3%).
CONCLUSION: The method performs favourably overall, particularly when long-term forecasts are required given short-term data
- …