Comparison between TCAD simulated and measured carrier lifetimes in CMOS photodiodes using the Open Circuit Voltage Decay method

The control and prediction of minority carrier lifetime are crucial for the design of photodiodes, especially for CMOS image sensors, because signal electrons must be captured before recombination. Analytic models have been developed but do not allow accurate and reliable lifetime estimations according to complex photodiode architecture. In this work, we show for the first time that mixed-mode TCAD simulations produce accurate and reliable results for realistic photodiode designs. To arrive at this conclusion, we have performed measurements and simulations on two different photodiodes using the Open Circuit Voltage Decay method

From EBIC Images to Qualitative Minority Carrier Diffusion Length Maps

A novel method is presented with the aim to perform minority carrier diffusion length map on cross-sectional samples. The method is based on one Electron-Beam Induced Current (EBIC) acquisition and on the analyze of the EBIC signal slope variation on each scanned points. This method is applied on a pinned photodiode array realized on a low doped silicon epitaxy, and the electron diffusion length map which is extracted is in good accordance with our expectation taking into account the doping distribution of the device. A TCAD simulation also confirms quantitatively the measured diffusion length map. Advantages and drawbacks of this method are discussed in this study

Exploration of Pinned Photodiode Radiation Hardening Solutions Through TCAD Simulations

The use of pinned photodiode (PPD) based CMOS image sensors in harsh radiation environment (such as space) is limited by their tolerance to ionizing radiation. Technology computer aided design (TCAD) simulations are performed to reproduce the radiation induced defect and therefore the dark current increase in pinned photodiode pixels up to 1 kGy (i.e. 100 krad) of total ionizing dose (TID). To do so, the TCAD models are calibrated with measurements performed on irradiated pixels. Then, the influence on the PPD radiation hardness of various manufacturing process and pixel design modifications is explored. This works shows that the proposed modification can improve the radiation hardness of pinned photodiode CMOS image sensors against ionizing

Plan View and Cross-Section View EBIC Measurements: Effect of e-Beam Injection Conditions on Extracted Minority Carrier Transport Properties

Application of low doped epitaxial layers and the increase of complexity of silicon photodiode design require the knowledge of the basic physical parameters such as minority carrier lifetime or diffusion length in order to improve the photodiode performance simulation. In this paper, EBIC technique is used to evaluate minority carrier lifetime and diffusion length on a silicon photodiode. Particular focus is to compare plan view and cross-section view testing geometry, and also to evaluate artefacts introduced by high injection conditions unavoidable in lifetime measurement

Influence of Pixel Design on Charge Transfer Performances in CMOS Image Sensors

The influence of pixel design on image lag is investigated by focusing on two different aspects which impact the charge transfer. First it is confirmed that the transfer gate channel doping profile strongly affects image lag. Introducing a step under the TG in the potential diagram, due to the doping implant differences in the channel, enables very good transfer performances by limiting spill-back of the charge to the photodiode. On the other hand, it is demonstrated that the overlap between the two implants used to create the step can produce a potential barrier under the transfer gate which extension increases the image lag. Then, the influence of pixel layout geometrical parameters (e.g. of the photodiode size, the transfer gate length and floating diffusion area) on the charge transfer efficiency is clarified. The whole study conclusions allow identifying the design parameter limiting the transfer efficiency in a given design and the possible design based solutions to improve it

Design Impact on Charge Transfer Inefficiency of Surface CCD on CMOS Devices: TCAD and Characterization Study

This work presents a study of design optimization of CCD on CMOS devices, in order to minimize the Charge Transfer Inefficiency (CTI). To achieve this goal, 3D Technology Computer Aided Design (TCAD) simulations with a trap model at silicon–oxide interface were conducted, and measurements on two test chips manufactured on two different foundries were performed. TCAD simulations predict trends in agreement with measurements, but trap models at STI and gate oxides should be adapted accordingly to the technology used. Some design variations show results depending on the technology chosen, and the best CTI reduction is obtained with an increase of Pwell inclusion over STI edges

Pinned Photodiode CMOS Image Sensor\\TCAD Simulation: in-Depth Analysis of in-Pixel Pinning Voltage Measurement for a Diagnostic Tool

TCAD simulations are conducted on a pinned photodiode (PPD), with the aim to reproduce the pinning voltage measurement developed by Tan \textit{et al}. A thermionic model is proposed and detailed in order to explain the exponential injection occurring at an injection voltage higher than the pinning voltage, and the correct method to extract the transfer gate inversion voltage is given. Then, various non idealities are simulated, such as doping variations or doping layer shifts, the goal being to get a PPD diagnostic tool based on the pinning voltage measurement. Finally, the pinned photodiode is simulated in a real reading mode, and a charge partition mechanism is demonstrated in specific conditions

Radiation Effects in Pinned Photodiode CMOS Image Sensors: Pixel Performance Degradation Due to Total Ionizing Dose

Several Pinned Photodiode (PPD) CMOS Image Sensors (CIS) are designed, manufactured, characterized and exposed biased to ionizing radiation up to 10 kGy(SiO2 ). In addition to the usually reported dark current increase and quantum efficiency drop at short wavelengths, several original radiation effects are shown: an increase of the pinning voltage, a decrease of the buried photodiode full well capacity, a large change in charge transfer efficiency, the creation of a large number of Total Ionizing Dose (TID) induced Dark Current Random Telegraph Signal (DC-RTS) centers active in the photodiode (even when the Transfer Gate (TG) is accumulated) and the complete depletion of the Pre-Metal Dielectric (PMD) interface at the highest TID leading to a large dark current and the loss of control of the TG on the dark current. The proposed mechanisms at the origin of these degradations are discussed. It is also demonstrated that biasing (i.e., operating) the PPD CIS during irradiation does not enhance the degradations compared to sensors grounded during irradiation

On The Pixel Level Estimation of Pinning Voltage, Pinned Photodiode Capacitance and Transfer Gate Channel Potential

The pinning voltage extraction method proposed by Tan et al. is analyzed to clarify its benefits and limitations. It is demonstrated that this simple measurement can bring much more useful information than the pinning voltage, such as the pinned photodiode capacitance and the transfer gate channel potential. Objective criteria to compare the pinning voltage on different devices are also discussed

Study of CCD Transport on CMOS Imaging Technology: Comparison Between SCCD and BCCD, and Ramp Effect on the CTI

This paper presents measurements performed on Charge Coupled Device (CCD) structures manufactured on a deep submicron CMOS imaging technology, in surface channel CCD and in buried channel CCD mode. The charge transfer inefficiency is evaluated for both CCD modes with regard to the injected charge, and the influence of the rising and falling time effect is explored. Controlling the ramp and especially reducing its abruptness allows to get much lower CTI in BCCD mode. In contrary, we did not observe any effect of the ramp on SCCD mode, due to the presence of interface traps at the silicon – oxide interface