Soft error analysis and mitigation in circuits involving C-elements

PhD ThesisA SEU or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption. The first part of this thesis studies the impact of process variation, temperature, voltage and size scaling within the same process on the vulnerability of the nodes of C-element circuits. The objectives are to identify vulnerable to SEU nodes inside a C-element and to find the critical charge needed to flip the output from low to high (0-1) and high to low (1-0) on different implementations of C-elements. In the second part, a framework to compute the SEU error rates is developed. The error rates of circuits are a trade-off between the size of the transistors and the total area of vulnerability. Comparisons of the vulnerability of different configurations of a C-element are made, and error rates are calculated. The third part focuses on soft error mitigation for single and dual rail latches. The latches are able to detect and correct errors due to SEU. The functionalities of the solutions have been validated by simulation. A comprehensive analysis of the performance of the latches under variations of the process and temperature are presented. The fourth part focuses on testing of the new latches. The objective is to design complex systems and incorporate both single rail and dual rail latches in the systems. Errors are injected in the latches and the functionality of the error correcting latches towards the SEU errors are observed at their outputs. The framework to compute error rates and soft error mitigation developed in this thesis can be used by designers in predicting the occurrence of soft error and mitigating soft error in systems

FPGA-based Implementation of SHA-256 with Improvement of Throughput using Unfolding Transformation

Security has grown in importance as a study issue in recent years. Several cryptographic algorithms have been created to increase the performance of these information-protecting methods. One of the cryptography categories is a hash function. This paper proposes the implementation of the SHA-256 (Secure Hash Algorithm-256) hash function. The unfolding transformation approach was presented in this study to enhance the throughput of the SHA- 256 design. The unfolding method is employed in the hash function by producing the hash value output based on modifying the SHA-256 structure. In this unfolding method, SHA- 256 decreases the number of clock cycles required for traditional architecture by a factor of two, from 64 to 34 because of the delay. To put it another way, one cycle of the SHA-256 design can generate up to four parallel inputs for the output. As a result, the throughput of the SHA-256 design can be improved by reducing the number of cycles by 16 cycles. ModelSim was used to validate the output simulations created in Verilog code. The SHA-256 hash function factor four hardware implementation was successfully tested using the Altera DE2-115 FPGA board. According to timing simulation findings, the suggested unfolding hash function with factor four provides the most significant throughput of around 4196.30 Mbps. In contrast, the suggested unfolding with factor two surpassed the classic SHA-256 design in terms of maximum frequency. As a result, the throughput of SHA-256 increases 13.7% compared to unfolding factor two and 58.1% improvement from the conventional design of SHA-256 design

Economic Dispatch Strategy for Solar Hybrid System using Lambda Iteration Method

A method for optimal power dispatch of hybrid system consisting of Solar-Diesel-Battery systems in remote area is presented. The aim of this paper is to provide a performance analysis of the method applied for cost reduction related to the constraint and satisfaction of load demand. The method presented utilizes the data and parameter of the Bario Solar Hybrid Central Station, Bario, Sarawak, Malaysia (3.7350° N, 115.4793° E). This work proposes a MATLAB software package to estimate optimal real power value with the least generating cost for the system. The operation, maintenance and investment costs are specified in the cost functions of the energy sources and will consider the assumption of equal incremental cost. Different case study has been carried out to solve the system equation and finally, the result from the proposed method is to be compared to a reduced gradient optimization method. It is found out the method in this study proved to be effective by giving an improved optimization results and efficiency for obtaining optimal power dispatch with few parameters in various tested conditions

Throughput Enhancement of the RIPEMD-160 Design Using the Unfolding Transformation Technique

Abstract: Many cryptographic applications use RIPEMD-160 hash functions, such as digital signatures, Hash Message Authentication Code (HMAC), and other data security applications. The suggested RIPEMD-160 designs are as follows: RIPEMD-160 iterative design, RIPEMD-160 unfolding with factor two, and RIPEMD-160 unfolding with factor four. These methodologies were applied to RIPEMD-160 designs in order to evaluate the inner structure of the design in terms of area, maximum frequency, and throughput. In this project, the RIPEMD-160 hash function was implemented with a high throughput utilising an unfolding transformation technique with a factor of four. The throughput of RIPEMD-160 unfolding design has been increased. The goal of the project is to improve the throughput of RIPEMD-160. The throughput of RIPEMD-160 was increased to around 1753.50 Mbps by applying the unfolding transformation factor four approach. When RIPEMD-160 unfolding with factor four designs is compared to other RIPEMD-160 designs, the percentage of performance to area ratio increases by 1.51%. In comparison to alternative designs, the results suggest that the proposed designs perform the best. ModelSim Altera-Quartus II simulation results were used to prove the accuracy of the RIPEMD-160 designs in terms of functional and timing simulations

High Speed and Throughput Evaluation of SHA-1 Hash Function Design with Pipelining and Unfolding Transformation Techniques

In recent years, designing of SHA-1 hash function has become popular because it was important in security design application. One of the applications of SHA-1 hash function was HMAC where the architecture of SHA-1 needed to be improved in terms of speed and throughput in order to obtain the highperformance design. The objective of this project was to design high speed and throughput evaluation of SHA-1 hash function based on a combination of pipelining and unfolding techniques. By using both techniques in designing the architecture of SHA- 1 design, the speed of SHA-1 hash function can be increased significantly as well as throughput of the design. In this paper, five proposed SHA-1 architectures were designed with different stages of pipelining such as 1, 4 and 40 stages. The results showed the high-speed design of SHA-1 design can be obtained by using 40 stages pipelining with unfolding factor two. This design provided a high-speed implementation with maximum frequency of 308.17 MHz on Arria II GX and 458.59 MHz on Virtex 5 XC5VLX50T. Furthermore, the throughput of the design also increased about 150.269 Gbps and 223.618 Gbps on Arria II GX and Virtex 5 XC5VLX50T respectively. Thus, highspeed design of SHA-1 hash function was successfully obtained which can give benefit to society especially in security system data transmission and other types of hash functions

The Impact of Soft Error On C-Element with Different Technology

This paper presents current injection resemble single event upset (SEU) current at the vulnerable nodes on Celements in particular Single Inverter with Inverter Latch (SIL) under two different technology 90nm and 180nm. C-element mainly uses in asynchronous circuits as the demand of consuming low power continue to become more important compared with synchronous circuits. However, one of the problems of asynchronous circuits is that they stay sensitive to SEU continuously for the whole cycle of operation. For asynchronous circuits, an acknowledgement signal is sent to the preceding register after the current operation is finished, indicating it is ready for the next operation. In the event of SEU hitting one of the registers, no acknowledgement signal is sent and therefore the preceding register does not assign the next operation to the current computational block. It is observed that the size of the transistor is the most important factors of critical charge variation since it has the highest standard deviation compared with temperature. This is due to the increasing the size of the transistors increases the gate capacitance from the output and therefore the collected charge needed to flip the output is also larger. However, as the size of the circuit is bigger, the probability of hitting by SEU is also increased even though the circuit is more resistant against SEU. The least significant factor is the temperature. As the temperature increased, the mobility of the carrier is reduced and degrades the performance of the transistor

Intelligent Greenhouse Monitoring and Control System Based Arduino UNO Microcontroller

Nowadays, there is a significant diminution in agricultural production due to the unpredictable control of crop climate conditions. Thus, to alleviate the crops exposure from excess cold or heat and unwanted pests, an intelligent environment monitoring and control system based Arduino UNO board consisting of ATmega 328P microcontroller has been developed for a small-scale agriculture namely greenhouse. The system user can monitor and control the greenhouse climate conditions remotely via web interface/mobile applications and GSM in a real-time manner. To deliver the environmental conditions in a timely manner, low-cost wireless sensor network (WSN) is used to monitor the temperature, humidity, soil moisture and light of the greenhouse. The sensor network constitutes a multi-hop network structure for large coverage. The developed system is implemented and tested in laboratory conditions using Proteus toolkit. Arduino Integrated Development Environment (IDE) tool is used to develop necessary software. The results show that the proposed system can closely monitor and evaluate greenhouse farming field conditions accurately. Finally, the user can send control decisions instantly to boost the yield growth conditions and thus, increase the crop production considerably

Towards Maximising Hardware Resources and Design Efficiency via High-Speed Implementation of HMAC based on SHA-256 Design

Some applications, such as Message Authentication Code (MAC), rely on different hashing operations. There are various hash functions, including Message-Digest 5 (MD5), RACE Integrity Primitives Evaluation Message Digest 160 (RIPEMD-160), Secure Hash Algorithm 1 (SHA-1), and Secure Hash Algorithm 256 (SHA-256), among others. The network layer is the third of seven layers of the Open Systems Interconnection (OSI) concept, also known as the Internet. It handles network addressing and physical data routing. Nowadays, enhanced internet security is necessary to safeguard networks from illegal surveillance. As a result, Internet Protocol Security (IPsec) introduces secure communication across the Internet by encrypting and/or authenticating network traffic at the IP level. IPsec is an internet-based security protocol. Encapsulating Security Payload (ESP) and Authentication Header (AH) protocols are separated into two protocols. The MAC value is stored in the authentication data files of the Authentication Header and Encapsulating Security Payload. This article analyses a fast implementation of the Hash-based Message Authentication Code (HMAC), which uses its algorithm to ensure the validity and integrity of data to optimise hardware efficiency and design efficacy using the SHA-256 algorithm. During data transfer, HMAC is critical for message authentication. It was successfully developed using Verilog Hardware Description Language (HDL) code with the implementation of a Field Programmable Gate Array (FPGA) device using the Altera Quartus II Computer-Aided Design (CAD) tool to enhance the maximum frequency of the design. The accuracy of the HMAC design, which is based on the SHA-256 design, was examined and confirmedusing ModelSim. The results indicate that the maximum frequency of the HMAC-SHA-256 design is approximately 195.16 MHz

The analysis of soft error in c-elements

Soft errors are a serious concern in state holders as it can cause temporarily malfunction of the circuit. C-element is one of the state holders that is used widely in the asynchronous circuit. In this paper, the investigation will focus on the vulnerability of two types of C-element towards soft errors. A framework has been proposed for the rate of error due to neutron spectrum energy that can cause failure in the state holder. Effective analysis has been conducted on two different C-elements at different nodes by using UMC90 nm technology and 180nm technology. Based on the vulnerability data, a method for assessing vulnerability on a different implementation of C-elements has been developed. From the obtained data, it can be concluded that SIL is more resistant towards soft errors. © 2018 Institute of Advanced Engineering and Science. All rights reserved