Soft error analysis and mitigation in circuits involving C-elements

PhD ThesisA SEU or soft error is defined as a temporary error on digital electronics due to the effect of radiation. Such an error can cause system failure, e.g. a deadlock in an asynchronous system or production of incorrect outputs due to data corruption. The first part of this thesis studies the impact of process variation, temperature, voltage and size scaling within the same process on the vulnerability of the nodes of C-element circuits. The objectives are to identify vulnerable to SEU nodes inside a C-element and to find the critical charge needed to flip the output from low to high (0-1) and high to low (1-0) on different implementations of C-elements. In the second part, a framework to compute the SEU error rates is developed. The error rates of circuits are a trade-off between the size of the transistors and the total area of vulnerability. Comparisons of the vulnerability of different configurations of a C-element are made, and error rates are calculated. The third part focuses on soft error mitigation for single and dual rail latches. The latches are able to detect and correct errors due to SEU. The functionalities of the solutions have been validated by simulation. A comprehensive analysis of the performance of the latches under variations of the process and temperature are presented. The fourth part focuses on testing of the new latches. The objective is to design complex systems and incorporate both single rail and dual rail latches in the systems. Errors are injected in the latches and the functionality of the error correcting latches towards the SEU errors are observed at their outputs. The framework to compute error rates and soft error mitigation developed in this thesis can be used by designers in predicting the occurrence of soft error and mitigating soft error in systems

Active Cell Balancing Control Method for Series-Connected Lithium-Ion Battery

Power conveyance potentiality for series and parallel allied battery-packages are constrained by the wickedest cell of the string. Every cell contains marginally dissimilar capability and terminal voltage because of industrialized acceptances and functional situations. During charging or discharging progression, the charge status of the cell strings become imbalanced and incline to loss equalization. Therefore, the enthusiasm of this paper is to design an active charge balancing system for Lithium-ion battery pack with the help of online state of charge (SOC) estimation technique. A Battery Management System (BMS) is modeled by means of controlling the SOC of the cells to upsurge the efficacy of rechargeable batteries. The capacity of each cell is calculated by dint of SOC function estimated as a result of Backpropagation Neural Network (BPNN) algorithm through four switched DC/DC Buck-Boost converter. The simulation results confirm that the designed BMS can synchronize the cell equalization via curtailing the SOC estimation error (RMSE 1.20%) productively

Development and Modelling of Three Phase Inverter for Harmonic Improvement using Sinusoidal Pulse Width Modulation (SPWM) Control Technique

This paper describes the design of a 400 V, three-phase voltage source inverter system using Sinusoidal Pulse Width Modulation (SPWM) control technique. Pulse Width Modulation (PWM) is an internal control technique for inverters. The Sinusoidal Pulse Width Modulation (SPWM) technique is the type of PWM used in this work. The aim is to reduce the harmonic produced by the inverter. Current standards require that total harmonic distortion (THD) be minimal. A three-phase SPWM signal is implemented in order to create an output voltage which is closer to a true sine wave and reduce harmonics. The development and model were implemented using MATLAB Simulink soft-ware and hardware parameters. The addition of a low pass filter circuit aids the achievement of smoother sine waveforms and a reduced THD value of 0.17%. The proposed concept has been validated through experimentally on a laboratory prototype by using DSP TMS320F28335 real-time digital control. The experimental outcomes emphasize the authenticity of the suggested technique in reducing harmonics, which can be promising to power quality improvement

The analysis of soft error in c-elements

Soft errors are a serious concern in state holders as it can cause temporarily malfunction of the circuit. C-element is one of the state holders that is used widely in the asynchronous circuit. In this paper, the investigation will focus on the vulnerability of two types of C-element towards soft errors. A framework has been proposed for the rate of error due to neutron spectrum energy that can cause failure in the state holder. Effective analysis has been conducted on two different C-elements at different nodes by using UMC90 nm technology and 180nm technology. Based on the vulnerability data, a method for assessing vulnerability on a different implementation of C-elements has been developed. From the obtained data, it can be concluded that SIL is more resistant towards soft errors. © 2018 Institute of Advanced Engineering and Science. All rights reserved

Voltage Tracking of a Multi-Input Interleaved Buck-Boost DC-DC Converter Using Artificial Neural Network Control

This paper proposes an artificial neural network (ANN) voltage tracking of multi-input interleaved buck-boost DC-DC converter. A back-propagation algorithm topology is implemented in this paper. The control unit is implemented to ameliorate the performance of the proposed multi-input converter during transient dynamic response and steady-state operation mode. The neural network controller unit design, which is adaptive against output voltage command tracking and reference voltage variations is proposed. The proposed design has been verified through the MATLAB software. The simulation outcomes emphasized the validity and reliability of the proposed neural network technique, which would be a promising an efficient control method that ensures multi-input converter suitable for electric vehicle and renewable energy application system

Simulation-Based Power Estimation for High Throughput SHA-256 Design on Unfolding Transformation

In recent years, security has grown in importance as a research topic. Several cryptographic SHA-256 hash algorithms have been developed to enhance the performance of data-protection techniques. In security system designs where data transmission must be properly encrypted to avoid eavesdropping and unwanted monitoring, the Hash Function is vital. In constructing the SHA-256 algorithm, high speed, compact size, and low power consumption are all factors to be taken into account for an efficient implementation. The purpose of this project is to reduce dynamic thermal power dissipation of SHA-256 unfolding transformation. State encoding is a method used in reducing power design strategies that have been proposed to lower the dynamic power dissipation of the algorithm. The algorithms are successfully designed using the Altera Quartus II platform. The ModelSim is used to test how accurate the results of simulations written in Verilog code are and to validate them. This study presents the unfolding transformation with Gray encoding approach to reduce the SHA-256 design's power consumption and increase its throughput. The SHA-256 unfolding transformation reduces the amount of clock cycles required for conventional architecture. In this research, the dynamic power SHA-256 unfolding factor 4 with Gray encoding reduces by 43.4 percent from Binary encoding with high throughput of the design. Therefore, it was suggested that to provide high performance of the embedded security system design, an unfolding transformation with Gray encoding design can be applied to the hash function design. Thus, the performance of the SHA-256 design can be greatly enhanced by changing the state encoding with the high number of unfolding factors. Based on this technology, the Power Analyzer in Altera Quartus II may produce an accurate simulation-based power assessment

Adaptive Algorithm for Optimal Route Configuration in Multi-Hop Wireless Sensor Network

Wireless Sensor Networks (WSNs) are best solutions for numerous aspects of engineering applications such as monitoring, control and surveillance of electrical plant amongst others. Autonomously, sensors will communicate with each other, collaborate, share and forward information in a multi-hop fashion without any centralized controller. To gather relevant data, the route optimization mechanism is used to solve the long routing problem and provide the shortest path amongst communicating nodes. Thus, this shortest path criterion is not suitable for WSN as it may lead to power drainage of several nodes and may cause high signaling and processing costs due to the network reconstruction. This paper proposes an optimal route configuration technique based on an adaptive genetic algorithm in which the architecture of multi-hop wireless sensor network is considered as a distributed computing infrastructure. The obtained results show that the proposed algorithm provides an optimal route configuration with the best performance in terms of evaluating the covered distance, packet loss and time delay

High Throughput Implementation of RIPEMD-160 using Unfolding Transformation

Cryptographic hash function is important for digital signature, Hash Message Authentication Code (HMAC) and other data security application. There are different types of hash function such as MD5, SHA-1, RIPEMD-160, SHA-2 and others. In this paper, RIPEMD-160 algorithm has been chosen as one of the hash functions because of the parallel inner structure of this algorithm. The objective of this research is to design and implement RIPEMD-160 with high throughput using different types of methodology. Three types of methodology are iterative, pipelining and unfolding design. These methodologies were applied to this RIPEMD-160 design in order to analyze the results of maximum frequency, area implementation and throughput of the design on Arria II GX FPGA family device. By using unfolding transformation, the throughput of the RIPEMD-160 can be improved which is about 1029.50 Mbps

Design and Implementation of a Voltage Tracking with Artificial Neural Network Controller for a Double-input Buck-Boost Converter

This paper proposes an Artificial Neural Network (ANN) control voltage tracking scheme of a double-input buckboost DC-DC converter. In this topology, a back-propagation algorithm topology is implemented. The controller is developed to improve the performance of the double-input converter during transient and steady-state operations. The neural network controller design, which is developed against output voltage command tracking is proposed. The proposed concept has been investigated and validated experimentally on a laboratory prototype using DSP TMS320F28335real time digital controller to verify the dynamic response of the proposed controller. The experimental results confirm the validity of the proposed neural network control technique, which is a promising an efficient control topology that ensures doubleinput converter suitable for electric vehicle and renewable energy applications

Synchrophasors Based Wide Area Protection and Phasor Estimation : A Review

Phasor Measurement Units (PMUs) are normally used in Wide Area Measurement System (WAMS) for vast applications, such as monitoring the transmission system status over bulky areas including the control and protection. Therefore, this paper reviews the power system protection in relation to the synchronized PMUs and the applications of phasor estimation techniques. Furthermore, the paper elaborates the research works on the applications of PMU for diverse features. The structure and types of PMUs are described utilizing the mathematical modeling of simple Discrete Fourier Transform (DFT) with Recursive and NonRecursive estimation methods. The paper also presents the results of some published studies for two algorithms (Recursive and Non-Recursive). The review has revealed that the NonRecursive algorithm is more accurate and gives robust estimation result