Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.Comment: 9 pages, 4 figures, *G.C.T. and A.P. contributed equally to this wor

Thermionic Emission as a tool to study transport in undoped nFinFETs

Thermally activated sub-threshold transport has been investigated in undoped triple gate MOSFETs. The evolution of the barrier height and of the active cross-section area of the channel as a function of gate voltage has been determined. The results of our experiments and of the Tight Binding simulations we have developed are both in good agreement with previous analytical calculations, confirming the validity of thermionic approach to investigate transport in FETs. This method provides an important tool for the improvement of devices characteristics.Comment: 3 pages, 3 figure, 1 tabl

Deep level investigation of InGaAs on InP layer

Deep level traps in lattice-matched In0.47Ga0.53As epitaxial layers grown by MBE on InP substrates have been studied by Deep Level Transient Spectroscopy (DLTS) on Al2O3/InGaAs Metal-Oxide-Semiconductor (MOS) capacitors. The impact of different surface passivation steps and a post-gate-deposition Forming Gas Annealing (FGA) has been studied. It is shown that spectra are dominated by a near mid gap electron trap in the depletion region, with activation energy in the range 0.37 eV to 0.42 eV. At the same time, a broad background distribution of interface states is found as well, which is significantly reduced by the FGA. Detailed carrier trapping studies have been carried out to identify the origin of the grown-in electron traps, which are shown to be of point defect behavior

Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |dEb/dVgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.Comment: 12 figures, 13 pages, Submitted to Journal of Applied Physic

Correlation between surface reconstruction and polytypism in InAs nanowire selective area epitaxy

Themechanism of widely observed intermixing of wurtzite and zinc-blende crystal structures in InAs nanowire (NW) grown by selective area epitaxy (SAE) is studied. We demonstrate that the crystal structure in InAs NW grown by SAE can be controlled using basic growth parameters, and wurtzitelike InAs NWs are achieved.We link the polytypic InAs NWs SAE to the reconstruction of the growth front (111)B surface. Surface reconstruction study of InAs (111) substrate and the following homoepitaxy experiment suggest that (111) planar defect nucleation is related to the (1 × 1) reconstruction of InAs (111)B surface. In order to reveal it more clearly, a model is presented to correlate growth temperature and arsenic partial pressure with InAs NW crystal structure. This model considers the transition between (1 × 1) and (2 × 2) surface reconstructions in the frame of adatom atoms adsorption/desorption, and the polytypism is thus linked to reconstruction quantitatively. The experimental data fit well with the model, which highly suggests that surface reconstruction plays an important role in the polytypism phenomenon in InAs NWs SAE.https://doi.org/10.1103/PhysRevMaterials.1.074603Peer Reviewe

An investigation on border traps in III-V MOSFETs with an In0.53Ga0.47As channel

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device timeto-failure projection

Observation of the stacking faults in In0.53Ga0.47As by electron channeling contrast imaging

The observation and interpretation of Frank stacking faults, Shockley stacking faults, Lomer dislocations, and 60 degrees misfit dislocations, which have similar line shapes in the (001) In0.53Ga0.47As crystalline surface, are performed with the electron channeling contrast imaging (ECCI) technique. To minimize the backscattered electron (BSE) contrast that resulted from the surface morphology, a relatively flat region is first selected and compared with an atomic force microscopy (AFM) image and then, subsequently, examining ECCI with transmission electron microscopy (TEM)-like invisibility criteria. By orthogonally choosing the diffraction vector g between (220) and (2-20), misfit dislocations seem to be always visible but partially faint in the g parallel to the line direction on the surface. With respect to the image contrast, Frank stacking faults and Lomer dislocations are likely to be completely invisible for parallel g. The criteria are further confirmed by cross-sectional TEM analysis, which shows a preferred homogeneous surface nucleation

Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling (“more Moore”) and functional scaling to enhance on-chip functionality (“more than Moore”)