Thermal decomposition mechanisms of hafnium and zirconium silicates at the atomic scale

The hafnium and zirconium silicates, (MO2)(x)(SiO2)(1-x), with M=Hf/Zr, are being considered as high-k gate dielectrics for field-effect transistors as a compromise between high permittivity and thermal stability during processing. Using atomic-scale models of silicates derived from hafnon/zircon, stability before and after simulated thermal annealing is calculated within a density-functional approach. These silicates are found to be thermodynamically unstable with respect to decomposition into SiO2 and MO2 (M=Hf/Zr). Segregation mechanisms on the atomic scale are studied leading to an insight as to an why SiO2-rich mixtures undergo spinodal decomposition and why, by contrast, MO2-rich phases are metastable, decomposing below typical process temperatures

Stress in silicon interlayers at the SiO(x)/Ge interface

Materials such as germanium display an advantage relative to silicon in terms of carrier mobilities but form poor quality interfaces to oxides. By sandwiching silicon layers between a germanium substrate and the oxide, advantages of the silicon oxide/silicon (SiO(x)/Si) interface can be retained combined with the advantage of a high mobility germanium substrate. Using density functional theory calculations, stress within the silicon interlayer is quantified for different interlayer thicknesses revealing that for up to three silicon layers, the stress in the interlayer is compensated for by the energy gained by forming silicon-oxygen bonds at the interface. (c) 2007 American Institute of Physics. (DOI:10.1063/1.2713122

Analysis of the breakdown spot spatial distribution in Pt/HfO2/Pt capacitors using nearest neighbor statistics

The breakdown spot spatial distribution in Pt/HfO2/Pt capacitors is investigated using nearest neighbor statistics in combination with more conventional estimation methods such as the point-event and event-event distance distributions. The spots appear as a random point pattern over the top metal electrode and arise as a consequence of significant localized thermal effects caused by the application of high-voltage ramped stress to the devices. The reported study mainly involves the statistical characterization of the distances between each failure site and the nearest, second nearest,... kth nearest event and the comparison with the corresponding theoretical distributions for a complete spatial randomness (CSR) process. A method for detecting and correcting deviations from CSR based on a precise estimation of the average point intensity and the effective damaged device area is proposed. (C) 2013 AIP Publishing LLC

Inversion in the In0.53Ga0.47As metal-oxide-semiconductor system: Impact of the In0.53Ga0.47As doping concentration

In0.53Ga0.47As metal-oxide-semiconductor (MOS) capacitors with an Al2O3 gate oxide and a range of n and p-type In0.53Ga0.47As epitaxial concentrations were examined. Multi-frequency capacitance-voltage and conductance-voltage characterization exhibited minority carrier responses consistent with surface inversion. The measured minimum capacitance at high frequency (1 MHz) was in excellent agreement with the theoretical minimum capacitance calculated assuming an inverted surface. Minority carrier generation lifetimes, sg, extracted from experimentally measured transition frequencies, xm, using physics based a.c. simulations, demonstrated a reduction in sg with increasing epitaxial doping concentration. The frequency scaled conductance, G/x, in strong inversion allowed the estimation of accurate Cox values for these MOS devices

Fabrication of HfO2 patterns by laser interference nanolithography and selective dry etching for III-V CMOS application

Nanostructuring of ultrathin HfO2 films deposited on GaAs (001) substrates by high-resolution Lloyd's mirror laser interference nanolithography is described. Pattern transfer to the HfO2 film was carried out by reactive ion beam etching using CF4 and O2 plasmas. A combination of atomic force microscopy, high-resolution scanning electron microscopy, high-resolution transmission electron microscopy, and energy-dispersive X-ray spectroscopy microanalysis was used to characterise the various etching steps of the process and the resulting HfO2/GaAs pattern morphology, structure, and chemical composition. We show that the patterning process can be applied to fabricate uniform arrays of HfO2 mesa stripes with tapered sidewalls and linewidths of 100 nm. The exposed GaAs trenches were found to be residue-free and atomically smooth with a root-mean-square line roughness of 0.18 nm after plasma etching

Scrutinizing pre- and post-device fabrication properties of atomic layer deposition WS₂ thin films

In this work, we investigate the physical and electrical properties of WS2 thin films grown by a plasma-enhanced atomic layer deposition process, both before and after device fabrication. The WS2 films were deposited on thermally oxidized silicon substrates using the W(NMe2)2(NtBu)2 precursor and a H2S plasma at 450 °C. The WS2 films were approximately 8 nm thick, measured from high-resolution cross-sectional transmission electron imaging, and generally exhibited the desired horizontal basal-plane orientation of the WS2 layers to the SiO2 surface. Hall analysis revealed a p-type behavior with a carrier concentration of 1.31 × 1017 cm−3. Temperature-dependent electrical analysis of circular transfer length method test structures, with Ni/Au contacts, yielded the activation energy (Ea) of both the specific contact resistivity and the WS2 resistivity as 100 and 91 meV, respectively. The similarity of these two values indicates that the characteristics of both are dominated by the temperature dependence of the WS2 hole concentration. Change in the material, such as in sheet resistance, due to device fabrication is attributed to the chemicals and thermal treatments associated with resist spinning and baking, ambient and UV exposure, metal deposition, and metal lift off for contact pad formation.</p

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hysteresis is taking place primarily in the interfacial oxide transition layer between the In0.53Ga0.47As and the ALD deposited oxide. Analysis of samples with a range of oxide thickness values also demonstrates that the magnitude of the C-V hysteresis window increases linearly with the increasing oxide thickness, and the corresponding trapped charge density is not a function of the oxide thickness, providing further evidence that the charge trapping is predominantly localised as a line charge and taking place primarily in the interfacial oxide transition layer located between the In0.53Ga0.47As and the high-k oxide. (C) 2013 AIP Publishing LLC

Diffusion of In0.53Ga0.47As elements through hafnium oxide during post deposition annealing

Diffusion of indium through HfO2 after post deposition annealing in N-2 or forming gas environments is observed in HfO2/In0.53Ga0.47As stacks by low energy ion scattering and X-ray photo electron spectroscopy and found to be consistent with changes in interface layer thickness observed by transmission electron microscopy. Prior to post processing, arsenic oxide is detected at the surface of atomic layer deposition-grown HfO2 and is desorbed upon annealing at 350 degrees C. Reduction of the interfacial layer thickness and potential densification of HfO2, resulting from indium diffusion upon annealing, is confirmed by an increase in capacitance. (C) 2014 AIP Publishing LLC

Wide spectral photoresponse of layered platinum diselenide-based photodiodes

Platinum diselenide (PtSe2) is a group-10 transition metal dichalcogenide (TMD) that has unique electronic properties, in particular a semimetal-to-semiconductor transition when going from bulk to monolayer form. We report on vertical hybrid Schottky barrier diodes (SBDs) of two-dimensional (2D) PtSe2 thin films on crystalline n-type silicon. The diodes have been fabricated by transferring large-scale layered PtSe2 films, synthesized by thermally assisted conversion of predeposited Pt films at back-end-of-the-line CMOS compatible temperatures, onto SiO2/Si substrates. The diodes exhibit obvious rectifying behavior with a photoresponse under illumination. Spectral response analysis reveals a maximum responsivity of 490 mA/W at photon energies above the Si bandgap and relatively weak responsivity, in the range of 0.1–1.5 mA/W, at photon energies below the Si bandgap. In particular, the photoresponsivity of PtSe2 in infrared allows PtSe2 to be utilized as an absorber of infrared light with tunable sensitivity. The results of our study indicate that PtSe2 is a promising option for the development of infrared absorbers and detectors for optoelectronics applications with low-temperature processing conditions

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−10.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−13.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−21.8×1012 cm−2 to 5.3×1011 cm−25.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−27.3×1011 cm−2 to 1.4×1012 cm−21.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge