Periodic scheduling of marked graphs using balanced binary words

This report presents an algorithm to statically schedule live and strongly connected Marked Graphs (MG). The proposed algorithm computes the best execution where the execution rate is maximal and place sizes are minimal. The proposed algorithm provides transition schedules represented as binary words. These words are chosen to be balanced. The contributions of this paper is the proposed algorithm itself along with the characterization of the best execution of any MG.Comment: No. RR-7891 (2012

Refining cellular automata with routing constraints

A cellular automaton (CA) is an infinite array of cells, each containing the same automaton. The dynamics of a CA is distributed over the cells where each computes its next state as a function of the previous states of its neighborhood. Thus, the transmission of such states between neighbors is considered as feasible directly, in no time. When considering the implementation of a cellular automaton on a many-cores System-on-Chip (SoC), this state transmission is no longer abstract and instantaneous, but has to follow the interconnection medium of the SoC. It is usually a grid or a mesh matching the underlying topology of the CA but finite. In order to consider such constraints at a higher level, we propose a refinement of the classical model of CA where the topology is considered as the communication medium. If the state of a cell depends on its neighbors up to a certain distance, then a given state must be broadcasted to all its neighbors at the same distance, as they all require it to compute their next state. It means routing and duplicating the state in the topology. We study the routing patterns needed to efficiently implement such state broadcasting algorithm. We provide a solution by which each router can locally predict where to redirect the states to correctly and efficiently implement this broadcasting algorithm.Un automate cellulaire (AC) est un tableau infini de cellules, chacune contenant le même automate. La dynamique d'un AC est distribuée entre les cellules, chacune calcule son prochain état comme une fonction des états de ses voisins. Donc, la transmission d'un état entre deux cellules est donc considérée comme faisable directement et instantanément. Quand on s'intéresse à l'implémentation d'un AC sur un système sur puce à plusieurs cores, on ne peut plus considérer la transmission d'un état comme une action abstraite et instantanée. Cette transmission doit suivre le medium d'interconnexion du système sur puce. Ce dernier est habituellement une grille ou un mesh (grille dans laquelle les extrémités opposées sont connectées) correspondant à la topologie logique de l'AC mais finie. Afin de prendre en compte la notion de medium d'interconnexion à un niveau d'abstraction supérieur, par rapport à l'implémentation, nous proposons un raffinement du modèle classique des AC dans lequel la topologie est considérée comme le medium d'interconnexion. Si l'état d'une cellule dépend de son entourage jusqu'à une certaine distance, alors cet état doit être diffusé à tous les voisins jusqu'à cette même distance puis ce que chacun d'eux en a besoin pour calculer son nouvel état. Cela signifie router et diffuser l'état en question dans la topologie. Nous étudions le schéma de routage nécessaire pour mettre en oeuvre efficacement cet algorithme de diffusion d'état. Dans cette solution, chaque router peut localement prédire où envoyer les états en transit afin de garantir la justesse de l'algorithme

Safe CCSL Specifications and Marked Graphs

International audienceThe Clock Constraint Specification Language (CCSL) proposes a rich polychronous time model dedicated to the specification of constraints on logical clocks: i.e., sequences of event occurrences. A priori independent clocks are progressively constrained through a set of clock operators that define when an event may occur or not. These operators can be described as labeled transition systems that can potentially have an infinite number of states. A CCSL specification can be scheduled by performing the synchronized product of the transition systems for each operator. Even when some of the composed transition systems are infinite, the number of reachable states in the product may still be finite: the specification is safe. The purpose of this paper is to propose a sufficient condition to detect that the product is actually safe. This is done by abstracting each CCSL constraint (relation and expression) as a marked graph. Detecting that some specific places, called counters, in the resulting marked graph are safe is sufficient to guarantee that the composition is safe

Refining cellular automata with routing constraints

A cellular automaton (CA) is an infinite array of cells, each containing the same automaton. The dynamics of a CA is distributed over the cells where each computes its next state as a function of the previous states of its neighborhood. Thus, the transmission of such states between neighbors is considered as feasible directly, in no time. When considering the implementation of a cellular automaton on a many-cores System-on-Chip (SoC), this state transmission is no longer abstract and instantaneous, but has to follow the interconnection medium of the SoC. It is usually a grid or a mesh matching the underlying topology of the CA but finite. In order to consider such constraints at a higher level, we propose a refinement of the classical model of CA where the topology is considered as the communication medium. If the state of a cell depends on its neighbors up to a certain distance, then a given state must be broadcasted to all its neighbors at the same distance, as they all require it to compute their next state. It means routing and duplicating the state in the topology. We study the routing patterns needed to efficiently implement such state broadcasting algorithm. We provide a solution by which each router can locally predict where to redirect the states to correctly and efficiently implement this broadcasting algorithm.Un automate cellulaire (AC) est un tableau infini de cellules, chacune contenant le même automate. La dynamique d'un AC est distribuée entre les cellules, chacune calcule son prochain état comme une fonction des états de ses voisins. Donc, la transmission d'un état entre deux cellules est donc considérée comme faisable directement et instantanément. Quand on s'intéresse à l'implémentation d'un AC sur un système sur puce à plusieurs cores, on ne peut plus considérer la transmission d'un état comme une action abstraite et instantanée. Cette transmission doit suivre le medium d'interconnexion du système sur puce. Ce dernier est habituellement une grille ou un mesh (grille dans laquelle les extrémités opposées sont connectées) correspondant à la topologie logique de l'AC mais finie. Afin de prendre en compte la notion de medium d'interconnexion à un niveau d'abstraction supérieur, par rapport à l'implémentation, nous proposons un raffinement du modèle classique des AC dans lequel la topologie est considérée comme le medium d'interconnexion. Si l'état d'une cellule dépend de son entourage jusqu'à une certaine distance, alors cet état doit être diffusé à tous les voisins jusqu'à cette même distance puis ce que chacun d'eux en a besoin pour calculer son nouvel état. Cela signifie router et diffuser l'état en question dans la topologie. Nous étudions le schéma de routage nécessaire pour mettre en oeuvre efficacement cet algorithme de diffusion d'état. Dans cette solution, chaque router peut localement prédire où envoyer les états en transit afin de garantir la justesse de l'algorithme

Another glance at Relay Stations in Latency-Insensitive Designs

We revisit the formal modeling of relay stations, which are specific connection elements used in the theory of Latency-Insensitive Design of Globally-Asynchronous/Locally-Synchronous systems. Relay stations are in charge of taking into account the physical mandatory latencies, while handling the regulation of signal/data traffic so as to avoid starvation, deadlock and congestion of local IP synchronous computation blocks. Since proposed by Carloni et al, the structure and behaviors of these relay stations have been amply characterized and analysed. But previous works never provided a fully formal and cycle-accurate description of these mechanisms, amenable to formal verification for instance (instead, mainly simulation models were developed). Due to the needed precision of the whole scheme we feel such a formal description might be needed. We describe such an attempt here. On its way, this work also led us to a number of (hopefully insightful) remarks on favorable and disfavorable graph topologies and initialization features, that are also reported here

Safe CCSL Specifications and Marked Graphs

International audienceThe Clock Constraint Specification Language (CCSL) proposes a rich polychronous time model dedicated to the specification of constraints on logical clocks: i.e., sequences of event occurrences. A priori independent clocks are progressively constrained through a set of clock operators that define when an event may occur or not. These operators can be described as labeled transition systems that can potentially have an infinite number of states. A CCSL specification can be scheduled by performing the synchronized product of the transition systems for each operator. Even when some of the composed transition systems are infinite, the number of reachable states in the product may still be finite: the specification is safe. The purpose of this paper is to propose a sufficient condition to detect that the product is actually safe. This is done by abstracting each CCSL constraint (relation and expression) as a marked graph. Detecting that some specific places, called counters, in the resulting marked graph are safe is sufficient to guarantee that the composition is safe

Formal Methods for Schedulings of Latency-Insensitive Designs

LID ( Latency-Insensitive Design) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behaviour is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: Relay-Stations (RS) and Shell-Wrappers (SW). Our first goal is to provide a formal modeling of RS and SW, that can then be formally verified. As turns out, resulting behaviour is k-periodic, thus amenable to static scheduling. Our second goal is to provide formal hardware modeling here also. It initially performs Throughput Equalization, adding integer latencies wherever possible; residual cases require introduction of Fractional Registers (FRs) at specific locations. Benchmark results are presented, run on our KPassa tool implementation

Application Architecture Adequacy through an FFT case study

International audienceApplication Architecture Adequacy (AAA) aims at tuning an application to a given hardware architecture. However it is still a difficult and error prone activity. As like as in Hardware/Software co-design, it requires a model of both the application and the architecture. With the new highly-parallel architectures, AAA should also allow a fast exploration of different software mapping granularity in order to leverage better the hardware resources without sacrifying too much productivity. The main contribution of this paper is to extract from a case study a methodology based on dataflow modeling to make the software both faster to develop and suited to the target. Then we show how this methodology can solve some of these issues