Restoring Reliability in Fault Tolerant Reconfigurable Systems

The new generations of SRAM-based FPGAdevices, built on nanometer technology, are thepreferred choice for the implementation ofreconfigurable computing platforms. However,smaller technological scales increase theirvulnerability to manufacturing imperfections andhence to the occurrence of electromigration.Moreover, the large internal RAM (for configurationpurposes or as embedded memory blocks) makesthem more prone to soft errors.The incorporation of self-reconfigurationcapabilities in recent FPGAs, allied to the use of softand hard microprocessor cores, facilitates the offsetof these vulnerabilities by enabling the developmentof self-restoring fault tolerant reconfigurablesystems. In the methodology presented in this paper,the embedded microprocessor is also responsible forthe implementation of online self-test-and-repairstrategies, based on modular redundancy and onself-reconfiguration. The detection of faults, causedby soft or hard errors, may be followed by repairingactions, depending on the fault type. This approachleads to smoother system degradation, extending itslifetime and improving its reliability

An integrated reusable remote laboratory to complement electronics teaching

The great majority of the courses on science and technology areas where lab work is a fundamental part of the apprenticeship was not until recently available to be taught at distance. This reality is changing with the dissemination of remote laboratories. Supported by resources based on new information and communication technologies, it is now possible to remotely control a wide variety of real laboratories. However, most of them are designed specifically to this purpose, are inflexible and only on its functionality they resemble the real ones. In this paper, an alternative remote lab infrastructure devoted to the study of electronics is presented. Its main characteristics are, from a teacher's perspective, reusability and simplicity of use, and from a students' point of view, an exact replication of the real lab, enabling them to complement or finish at home the work started at class. The remote laboratory is integrated in the Learning Management System in use at the school, and therefore, may be combined with other web experiments and e-learning strategies, while safeguarding security access issues

Techniques to improve the reliability of fault-tolerant systems based on self-reconfigurable FPGAs

In this paper it is proposed a new technique toimprove the reliability of fault-tolerant systemsbased on self-reconfigurable FPGAs. The aim is tocreate a self-tolerant system based on selfreconfiguration.To achieve this objective the workwas divided in five main tasks: the analysis of faultinducement mechanisms in FPGAs, its correlationand its matching with existent fault models, or,eventually, if necessary, the proposal of a newmodel; the design and evaluation of a fault tolerancemechanism for FPGAs; the design andimplementation of a methodology able to detect,diagnose and repair the emerging faults; thedevelopment and validation of the proposedmethodology. This study will be the base for a PhDthesis

An integrated framework to support remote IEEE 1149.1 /1149.4 design for test experiments

Remote experiments for academic purposes can only achieve their educational goals if an appropriate framework is able to provide a basic set of features, namely remote laboratory management, collaborative learning tools and content management and delivery. This paper presents a framework developed to support remote experiments in a design for test class offered to final year students at the Electrical and Computer Engineering degree at the University of Porto. The proposed solution combines a test language command interpreter and various virtual instruments (VIs), with a demonstration board that comprises a boundary-scan IEEE 1149.1 / 1149.4 test infrastructure. The experiments are presented as embedded learning objects, with no distinction from other e-learning contents (e.g. lessons, lecture notes, etc.)

Improved dependability for dynamically reconfigurable hardware: restoration of the reliability index via replication and error correction

Fault-tolerant (FT) architectures based on classic spatial and temporal redundancy are used in anincreasing number of applications. However, the hardware platforms underlying modern highreliabilitysystems have little resemblance to those that were common when such architectureswere devised. The earlier fault models are not necessarily out-of-date (e.g. stuck-at faults stillplay an important role for validating FT applications), but the new failure modes of nanometertechnologies were largely irrelevant when J. von Neumanns paper on the synthesis of reliableorganisms from unreliable components was published in the 1950s. Such concerns areparticularly relevant when designing high-reliability adaptive systems, where reconfigurablefield-programmable gate arrays (FPGAs) are increasingly used. On the other hand, theeconomics of FT architectures based on spatial redundancy (e.g. triple modular redundancy,TMR), are entirely different when evaluated under the assumption of such features as dynamicreconfiguration, which enables just-in-time implementation of only those resources that need tobe available at any given time, or self-reconfiguration, which enables self-contained correctiveactions that are able to isolate / replace defective resources. New design approaches are therefore required to cope with the challenges introduced by each new generation ofprogrammable hardware devices. This paper presents an approach to design high-reliabilityarchitectures at lower cost, by taking advantage of dynamic / self reconfiguration and built-intest infrastructures, which are present in modern generations of FPGAs

Run-time management of logic resources on reconfigurable systems

Dynamically reconfigurable systems based on partialand dynamically reconfigurable FPGAs may have theirfunctionality partially modified at run-time withoutstopping the operation of the whole system.The efficient management of the logic space availableis one of the biggest problems faced by these systems.When the sequence of reconfigurations to be performed isnot predictable, resource allocation decisions have to bemade on-line. A rearrangement may be necessary to getenough contiguous space to implement incomingfunctions, avoiding the spreading of their components andthe resulting degradation of system performance.A new software tool that helps to handle the problemsposed by the consecutive reconfiguration of the same logicspace is presented in this paper. This tool uses a novel on--line rearrangement procedure to solve fragmentationproblems and to rearrange the logic space in a waycompletely transparent to the applications currentlyrunnin

A novel methodology for the concurrent test of partial and dynamically reconfigurable SRAM-based FPGAs

This poster presents the first truly non-intrusive structural concurrent test approach, with the objective of testing partially and dynamically reconfigurable SRAM-based FPGAs without disturbing their operation. This is accomplished by using a new methodology to carry out the replication of active Configurable Logic Blocks (CLBs), i.e. CLBs that are part of an implemented function that is actually being used by the system, releasing it to be tested in a way that is completely transparent to the system

A Framework for implementing radiation-tolerant circuits on reconfigurable FPGAs

The outstanding versatility of SRAM-based FPGAs make them the preferred choice for implementing complex customizable circuits. To increase the amount of logic available, manufacturers are using nanometric technologies to boost logic density and reduce prices. However, the use of nanometric scales also makes FPGAs particularly vulnerable to radiation-induced faults, especially because of the increasing amount of configuration memory cells that are necessary to define their functionality. This paper describes a framework for implementing circuits immune to radiation-induced faults, based on a customized Triple Modular Redundancy (TMR) infrastructure and on a detection-and-fix controller. This controller is responsible for the detection of data incoherencies, location of the faulty module and restoration of the original configuration, without affecting the normal operation of the mission logic. A short survey of the most recent data published concerning the impact of radiation-induced faults in FPGAs is presented to support the assumptions underlying our proposed framework. A detailed explanation of the controller functionality is also provided, followed by an experimental case study

Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections

Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation of the whole system. The efficient management of the logic space available is one of the biggest problems faced by these systems. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. A rearrangement may be necessary to get enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance.A new software tool that helps to handle the problems posed by the consecutive reconfiguration of the same logic space is presented in this paper. This tool uses a novel on-line rearrangement procedure to solve fragmentation problems and to rearrange the logic space in a way completely transparent to the applications currently running

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead