Development of a triple well CMOS MAPS device with in-pixel signal processing and sparsified readout capabilities

none 39 The SLIM5 collaboration has designed, fabricated and tested several prototypes of CMOS Monolithic Active Pixel Sensors (MAPS). The key feature of these devices, with respect to traditional MAPS is to include, at the pixel level, charge amplification and shaping and a first sparsification structure that interfaces with on-chip digital readout circuits. Via the 3-well option of the applied View the MathML source ST-Microelectronics CMOS technology each pixel includes a charge preamplifier, a shaper, a discriminator, an output latch, while retaining a fill factor of the sensitive area close to 90%. The last device of the family was submitted on Q4 2006 and the tests are ongoing. On this sensor, an on-chip, off-pixel digital readout block (streamout data sparsification) was added to implement, to control and to readout a test matrix built up of 4×4 pixels. It is aimed at proposing solutions that will overcome the readout speed limit of future large-matrix MAPS chips. http://dx.doi.org/10.1016/j.nima.2007.07.135 none G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vitale G. Batignani; S. Bettarini; F. Bosi; G. Calderini; R. Cenci; M. Dell'Orso; F. Forti P. ; M.A. Giorgi; A. Lusiani; G. Marchiori; F. Morsani; N. Neri; E. Paoloni; G. Rizzo1; J. Walsh; L. Gaioni; M. Manghisoni; V. Re; G. Traversi; M. Bruschi; A. Gabrielli; B. Giacobbe; N. Semprini; R. Spighi; M. Villa; A. Zoccoli; G. Verzellesi; C. Andreoli5; E. Pozzati; L. Ratti; V. Speziali; D. Gamba; G. Giraudo; P. Mereu; L. Bosisio; G. Giacomini; L. Lanceri; I. Rachevskaia; L. Vital

Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades

MAPS in 130 nm triple well CMOS technology for HEP applications

Deep N-well CMOS monolithic active pixel sensors (DNWMAPS) represent an alternative approach to signal processing in pixellated detectors for high energy physics experiments. Based on different resolution constraints, two prototype MAPS, suitable for applications requiring different detector pitch, have been developed and fabricated in 130 nm triple well CMOS technology. This work presents experimental results from the characterization of some test structures together with TCAD and Monte Carlo simulations intended to study the device properties in terms of charge diffusion and charge sharing among pixels

PixFEL: development of an X-ray diffraction imager for future FEL applications

A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm. Each cell includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, covering an input dynamic range from 1 to 104 photons and featuring single photon resolution at small signals at energies from 1 to 10 keV. The CSA output is processed by a time-variant shaper performing gated integration and correlated double sampling. Each pixel includes also a small area, low power 10-bit time-interleaved Successive Approximation Register (SAR) ADC for in-pixel digitization of the amplitude measurement. The channel can be operated at rates up to 4.5 MHz, to be compliant with the rates foreseen for future X-ray FEL machines. The ASIC has been designed in order to be bump bonded to a slim/active edge pixel sensor, in order to build the first demonstrator for the PixFEL (advanced X-ray PIXel cameras at FELs) imager

A 64k pixel CMOS-DEPFET module for the soft X-rays DSSC imager operating at MHz-frame rates

: The 64k pixel DEPFET module is the key sensitive component of the DEPFET Sensor with Signal Compression (DSSC), a large area 2D hybrid detector for capturing and measuring soft X-rays at the European XFEL. The final 1-megapixel camera has to detect photons with energies between [Formula: see text] and [Formula: see text], and must provide a peak frame rate of [Formula: see text] to cope with the unique bunch structure of the European XFEL. This work summarizes the functionalities and properties of the first modules assembled with full-format CMOS-DEPFET arrays, featuring [Formula: see text] hexagonally-shaped pixels with a side length of 136 μm. The pixel sensors utilize the DEPFET technology to realize an extremely low input capacitance for excellent energy resolution and, at the same time, an intrinsic capability of signal compression without any gain switching. Each pixel of the readout ASIC includes a DEPFET-bias current cancellation circuitry, a trapezoidal-shaping filter, a 9-bit ADC and a 800-word long digital memory. The trimming, calibration and final characterization were performed in a laboratory test-bench at DESY. All detector features are assessed at [Formula: see text]. An outstanding equivalent noise charge of [Formula: see text]e-rms is achieved at 1.1-MHz frame rate and gain of 26.8 Analog-to-Digital Unit per keV ([Formula: see text]). At [Formula: see text] and [Formula: see text], a noise of [Formula: see text] e-rms and a dynamic range of [Formula: see text] are obtained. The highest dynamic range of [Formula: see text] is reached at [Formula: see text] and [Formula: see text]. These values can fulfill the specification of the DSSC project

Large-area Si(Li) Detectors for X-ray Spectrometry and Particle Tracking for the GAPS Experiment

Large-area lithium-drifted silicon (Si(Li)) detectors, operable 150{\deg}C above liquid nitrogen temperature, have been developed for the General Antiparticle Spectrometer (GAPS) balloon mission and will form the first such system to operate in space. These 10 cm-diameter, 2.5 mm-thick multi-strip detectors have been verified in the lab to provide <4 keV FWHM energy resolution for X-rays as well as tracking capability for charged particles, while operating in conditions (~-40{\deg}C and ~1 Pa) achievable on a long-duration balloon mission with a large detector payload. These characteristics enable the GAPS silicon tracker system to identify cosmic antinuclei via a novel technique based on exotic atom formation, de-excitation, and annihilation. Production and large-scale calibration of ~1000 detectors has begun for the first GAPS flight, scheduled for late 2021. The detectors developed for GAPS may also have other applications, for example in heavy nuclei identification

CMOS monolithic sensors in a homogeneous 3D process for low energy particle imaging

A 3D, through silicon via microelectronic process, capable of face-to-face assembling two 130 nm CMOS tiers in a single bi-layer wafer, has been exploited for the design of monolithic active pixels (MAPS), featuring a deep N-well (DNW) collecting electrode. They are expected to improve on planar CMOS DNW MAPS in terms of charge collection efficiency since most of the PMOS transistors in the front-end electronics, with their N-wells, can be moved to a different layer from that of the DNW sensor. The vertical integration process also requires that one of the two CMOS tiers be thinned down to a mere 6 m to expose the through silicon vias and contact the sandwiched circuits. In this work, results from device simulations of 3D MAPS will be presented. The aim is to evaluate the potential of such a thin sensitive substrate in the detection of low energy particles (in the tens of keV range), in view of possible applications to biomedical imaging

Initial test results of an ionization chamber shower detector for a LHC luminosity monitor

A novel, segmented, multi-gap, pressurized gas ionization chamber is being developed for optimization of the luminosity of the LHC. The ionization chambers are to be installed in the front quadrupole and zero degree neutral particle absorbers in the high luminosity IRs and sample the energy deposited near the maxima of the hadronic/electromagnetic showers in these absorbers. The ionization chambers are instrumented with low noise, fast, pulse shaping electronics to be capable of resolving individual bunch crossings at 40 MHz. In this paper we report the initial results of our second test of this instrumentation in an SPS external proton beam. Single 300 GeV protons are used to simulate the hadronic/electromagnetic shower produced by the forward collision products from the interaction regions of the LHC. The capability of instrumentations to measure the luminosity of individual bunches in a 40 MHz bunch train is demonstrated

Comments by the Senior Editor

n/